Patents in Class 257/371

Matches 1 - 50 out of 496

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Match	Document	Document Title
1	7625791	High-k dielectric metal gate device structure and method for forming the same A metal gate/high-k dielectric semiconductor device provides an NMOS gate structure and a PMOS gate structure formed on a semiconductor substrate. The NMOS gate structure includes a high-k gate...
2	7615827	Dual gate dielectric thickness devices and circuits using dual gate dielectric thickness devices Dual thickness devices and circuits using dual gate thickness devices. The devices include: one or more FETs of a first polarity and one or more FETs of a second and opposite polarity, the one or...
3	7612422	Structure for dual work function metal gate electrodes by control of interface dipoles Exemplary embodiments provide structures for dual work function metal gate electrodes. The work function value of a metal gate electrode can be increased and/or decreased by disposing various...
4	7612415	Method of forming semiconductor device Embodiments relate to a method of forming a 90 nm semiconductor device, including forming an isolation film within a semiconductor substrate in which a pMOS region and an nMOS region are defined. A...
5	7608912	Technique for creating different mechanical strain in different CPU regions by forming an etch stop layer having differently modified intrinsic stress The present invention provides a technique for reducing stress or stress gradients in highly sensitive device regions, such as cache areas, while still providing high transistor performance in...
6	7608895	Modular CMOS analog integrated circuit and power technology A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms...
7	7608897	Sub-surface region with diagonal gap regions Diagonal deep well region for routing the body-bias voltage for MOSFETS in surface well regions is provided and described.
8	7608896	Semiconductor device A semiconductor device has an n-channel MIS transistor and a p-channel MIS transistor on a substrate. The n-channel MIS transistor includes a p-type semiconductor region formed on the substrate, a...
9	7605433	Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms...
10	7605432	Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms...
11	7605429	Hybrid crystal orientation CMOS structure for adaptive well biasing and for power and performance enhancement The present invention provides a semiconducting structure including a substrate having an SOI region and a bulk-Si region, wherein the SOI region and the bulk-Si region have a same or differing...
12	7602023	Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms...
13	7602024	Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms...
14	7598545	Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled CMOS devices The present invention is directed to CMOS structures that include at least one nMOS device located on one region of a semiconductor substrate; and at least one pMOS device located on another region...
15	7592675	Partial FinFET memory cell A semiconductor structure includes a semiconductor substrate, a planar PMOS device at a surface of the semiconductor substrate, and an NMOS device at the surface of the semiconductor substrate,...
16	7589386	Semiconductor device and manufacturing method thereof A semiconductor device including a first field effect transistor having a source, a first conductivity type drain, a gate, and a first conductivity type channel layer formed beneath the gate and...
17	7582522	Method and device for CMOS image sensing with separate source formation A method and device for image sensing. The method includes forming a first well and a second well in a substrate, forming a gate oxide layer on the substrate, and depositing a first gate region and...
18	7573104	CMOS device on hybrid orientation substrate comprising equal mobility for perpendicular devices of each type Embodiments herein present device, method, etc. for a hybrid orientation scheme for standard orthogonal circuits. An integrated circuit of embodiments of the invention comprises a hybrid...
19	7560782	Transistor structure with high input impedance and high current capability An integrated transistor device is formed in a chip of semiconductor material having an electrical-insulation region delimiting an active area accommodating a bipolar transistor of vertical type...
20	7560779	Method for forming a mixed voltage circuit having complementary devices A mixed voltage circuit is formed by providing a substrate ( 12 ) having a first region ( 20 ) for forming a first device ( 106 ), a second region ( 22 ) for forming a second device ( 108 )...
21	7547951	Semiconductor devices having nitrogen-incorporated active region and methods of fabricating the same A semiconductor device may include a semiconductor substrate having a first region and a second region. The nitrogen-incorporated active region may be formed within the first region. A first gate...
22	7547592	PMOS depletable drain extension made from NMOS dual depletable drain extensions In accordance with an embodiment of the invention, there is an integrated circuit device having a complementary integrated circuit structure comprising a first MOS device. The first MOS device...
23	7545004	Method and structure for forming strained devices A method for manufacturing a device includes mapping extreme vertical boundary conditions of a mask layer based on vertical edges of a deposited first layer and a second layer. The mask layer is...
24	7545005	Semiconductor device capable of avoiding latchup breakdown resulting from negative variation of floating offset voltage A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper...
25	7545001	Semiconductor device having high drive current and method of manufacture therefor A semiconductor device including an isolation region located in a substrate, an NMOS device located partially over a surface of the substrate, and a PMOS device isolated from the NMOS device by the...
26	7538396	Semiconductor device and complementary metal-oxide-semiconductor field effect transistor A semiconductor device includes a substrate, an epitaxial layer, a sinker, an active device, a first buried layer, and a second buried layer. The substrate has a first type conductivity. The...
27	7528450	Semiconductor device having NMOSFET and PMOSFET and manufacturing method therefor A element isolation insulating film is formed around the device regions in the silicon substrate. The device regions are formed an n-type diffusion layer region, a p-type diffusion layer region, a...
28	7528439	Vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by a process in which source, drain and...
29	7521741	Shielding structures for preventing leakages in high voltage MOS devices A high-voltage MOS device includes a first high-voltage well (HVW) region overlying a substrate, a second HVW region overlying the substrate, a third HVW region of an opposite conductivity type as...
30	7521325	Semiconductor device and method for fabricating the same A permeation preventing film of a silicon nitride film 16 is inserted between a silicon substrate 10 and a High-k gate insulation film 18 to thereby prevent the High-k gate insulation film ...
31	7514728	Semiconductor integrated circuit device using four-terminal transistors In a semiconductor substrate of a first conductivity type, a first well region of the first conductivity type, second well regions of a second conductivity type, and a third well region of the...
32	7514755	Integrated circuit modification using well implants A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed having a well of a first conductivity type under the gate region being...
33	7511347	Semiconductor integrated circuit for high-speed, high-frequency signal transmission A semiconductor integrated circuit comprising: a pair of MOS transistors which are formed in a same well on a semiconductor substrate and arranged adjacent to each other with a distance such that...
34	7511348	MOS transistors with selectively strained channels The channels of first and second CMOS transistors can be selectively stressed. A gate structure of the first transistor includes a stressor that produces stress in the channel of the first...
35	7504693	Dislocation free stressed channels in bulk silicon and SOI CMOS devices by gate stress engineering Structures and methods of manufacturing are disclosed of dislocation free stressed channels in bulk silicon and SOI (silicon on insulator) CMOS (complementary metal oxide semiconductor) devices by...
36	7495291	Strained dislocation-free channels for CMOS and method of manufacture A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. An SiGe layer is grown in the channel of the nFET...
37	7485931	Semiconductor integrated circuit A semiconductor integrated circuit has complementary field-effect transistors, one formed in a semiconductor substrate, the other formed in a well in the substrate, and has four power-supply...
38	7482657	Balanced cells with fabrication mismatches that produce a unique number generator A static random access memory (SRAM) is laid out to be balanced so that, when power is applied to the SRAM, the cells of the SRAM have no preferred logic state. In addition, the SRAM is fabricated...
39	7482671	MOS semiconductor device isolated by a device isolation film A MOS semiconductor device isolated by a trench device isolation region includes a p-channel MOS field effect transistor having a source/drain region with a length in the channel direction that is...
40	7442996	Structure and method for enhanced triple well latchup robustness Disclosed is a triple well CMOS device structure that addresses the issue of latchup by adding an n+ buried layer not only beneath the p-well to isolate the p-well from the p− substrate but also...
41	7439124	Method of manufacturing a semiconductor device and semiconductor device Method of manufacturing a semiconductor device includes: forming a substrate protection film to cover an n-type FET forming region having a first gate electrode and a p-type FET forming region...
42	7439590	Semiconductor device A semiconductor device features connecting gate patterns of all transistors to a N+ or +P junction by the first connected wiring layer to prevent degradation of characteristics of the semiconductor...
43	7439140	Formation of standard voltage threshold and low voltage threshold MOSFET devices Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked,...
44	7432553	Structure and method to optimize strain in CMOSFETs A semiconductor structure of strained MOSFETs, comprising both PMOSFETs and NMOSFETS, and a method for fabricating strained MOSFETs are disclosed that optimize strain in the MOSFETs, and more...
45	7423319	LDPMOS structure with enhanced breakdown voltage A semiconductor structure includes a first well region of a first conductivity type overlying a substrate, a second well region of a second conductivity type opposite the first conductivity type...
46	7420250	Electrostatic discharge protection device having light doped regions Provided are an electrostatic discharge (ESD) protection device and a method for making such a device. In one example, the ESD protection device includes a Zener diode region formed in a substrate...
47	7414293	Structure and method of applying localized stresses to the channels of PFET and NFET transistors for improved performance A semiconductor device has an n channel conductivity type field effect transistor having a channel formation region formed in a first region on one main surface of a semiconductor substrate and a p...
48	7412122	Integrated multichannel laser driver and photodetector receiver An integrated circuit cast on a single die having a plurality of receivers in a receiver region, a plurality of transmitters in a transmitter region, and a spatial separation region having a...
49	7410855	Semiconductor device A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode...
50	7411253	CMOS transistors using gate electrodes to increase channel mobilities by inducing localized channel stress A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel...

Matches 1 - 50 out of 496

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