Patents in Class 257/369

Matches 1 - 50 out of 1116

Match	Document	Document Title
1	7622755	Primitive cell that is robust against ESD A primitive cell having a gate pattern that is robust against ESD is provided. The primitive cell comprises: a high finger PMOS transistor and a low finger NMOS transistor. The high finger PMOS...
2	7619285	Method of fabricating CMOS transistor and CMOS transistor fabricated thereby A CMOS transistor includes first and second conductivity type MOS transistors. The first conductivity type MOS transistor includes elevated source and drain regions which abut a channel region in a...
3	7615831	Structure and method for fabricating self-aligned metal contacts A semiconductor structure including at least one transistor is provided which has a stressed channel region that is a result of having a stressed layer present atop a gate conductor that includes a...
4	7615433	Double anneal with improved reliability for dual contact etch stop liner scheme A method for forming a device with both PFET and NFET transistors using a PFET compressive etch stop liner and a NFET tensile etch stop liner and two anneals in a deuterium containing atmosphere....
5	7612414	Overlapped stressed liners for improved contacts A semiconductor structure is provided which includes a first semiconductor device in a first active semiconductor region and a second semiconductor device in a second active semiconductor region. A...
6	7612413	Semiconductor device and manufacturing method thereof A semiconductor device includes a substrate, a p-channel MIS transistor formed on the substrate, the p-channel MIS transistor having a first gate electrode, and an n-channel MIS transistor formed...
7	7608912	Technique for creating different mechanical strain in different CPU regions by forming an etch stop layer having differently modified intrinsic stress The present invention provides a technique for reducing stress or stress gradients in highly sensitive device regions, such as cache areas, while still providing high transistor performance in...
8	7608897	Sub-surface region with diagonal gap regions Diagonal deep well region for routing the body-bias voltage for MOSFETS in surface well regions is provided and described.
9	7608896	Semiconductor device A semiconductor device has an n-channel MIS transistor and a p-channel MIS transistor on a substrate. The n-channel MIS transistor includes a p-type semiconductor region formed on the substrate, a...
10	7608891	Thin film transistor, circuit apparatus and liquid crystal display A thin film transistor includes a one conductive type semiconductor layer ( 11 ); a source region ( 12 ) and a drain region ( 13 ) which are separately provided in the semiconductor layer; and a...
11	7608873	Buried-gated photodiode device and method for configuring and operating same A 3-T buried-gated photodiode device that is suitable for use in a windowed array. The 3-T buried-gated photodiode device is configured such that the floating diffusion (FD) node of the device is...
12	7608499	Semiconductor structure comprising field effect transistors with stressed channel regions and method of forming the same A method of forming a semiconductor structure comprises providing a semiconductor substrate comprising a first transistor element and a second transistor element. Each of the first transistor...
13	7605414	MOS transistors having low-resistance salicide gates and a self-aligned contact between them A method for forming a self-aligned contact between two MOS transistors is described. The method supports the use of low-resistivity suicides for the formation of contacts in nanometer applications...
14	7602031	Method of fabricating semiconductor device, and semiconductor device Disclosed is a method of fabricating a semiconductor device that includes field effect transistors each having a gate electrode formed only of a metal silicide which overcomes the problem of...
15	7598573	Systems and methods for voltage distribution via multiple epitaxial layers Systems and methods for voltage distribution via multiple epitaxial layers. In accordance with a first embodiment of the present invention, an integrated circuit comprises a wafer substrate of a...
16	7598540	High performance CMOS devices comprising gapped dual stressors with dielectric gap fillers, and methods of fabricating the same The present invention relates to complementary metal-oxide-semiconductor (CMOS) devices having gapped dual stressors with dielectric gap fillers. Specifically, each CMOS device of the present...
17	7592674	Semiconductor device with silicide-containing gate electrode and method of fabricating the same There is provided a semiconductor device which is capable of solving a problem of threshold control in CMOS transistor, accompanied with combination of a gate insulating film having a high...
18	7589386	Semiconductor device and manufacturing method thereof A semiconductor device including a first field effect transistor having a source, a first conductivity type drain, a gate, and a first conductivity type channel layer formed beneath the gate and...
19	7589385	Semiconductor CMOS transistors and method of manufacturing the same A CMOS transistor device including a tensile-stressed NMOS transistor and a PMOS transistor is disclosed. The NMOS transistor includes a gate, a gate oxide layer between the gate and semiconductor...
20	7586160	Method of manufacturing a semiconductor integrated circuit and semiconductor integrated circuit A semiconductor integrated circuit is provided in which a CMOS transistor is formed on a first conductivity type semiconductor film provided on a first conductivity type supporting substrate...
21	7586159	Semiconductor devices having different gate dielectrics and methods for manufacturing the same A semiconductor device includes first and second transistor devices. The first device includes a first substrate region, a first gate electrode, and a first gate dielectric. The first gate...
22	7586158	Piezoelectric stress liner for bulk and SOI A preferred embodiment of the invention provides a semiconductor device. A preferred device comprises an n-channel transistor and a p-channel transistor disposed in a semiconductor body and a...
23	7582927	Flash EEPROM cell and method of fabricating the same A semiconductor device including a memory cell having a memory transistor and select gate transistor and a peripheral transistor is disclosed. The memory transistor has a stacked gate structure...
24	7579660	Semiconductor device and manufacturing method thereof A semiconductor device includes a substrate including a semiconductor layer at a surface, a gate insulating film disposed on the semiconductor layer, and a gate electrode disposed on the gate...
25	7579655	Transistor structure having interconnect to side of diffusion and related method A transistor structure is disclosed including at least one transistor including a diffusion and an interconnect electrically connected to a side of the diffusion and a conductor in electrical...
26	7577040	Dual port memory device with reduced coupling effect A dual port SRAM cell includes at least one pair of cross-coupled inverters connected between a power line and complementary power line. A number of pass gate transistors connect the cross-coupled...
27	7576397	Semiconductor device A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode...
28	7575975	Method for forming a planar and vertical semiconductor structure having a strained semiconductor layer Forming a semiconductor structure includes providing a substrate having a strained semiconductor layer overlying an insulating layer, providing a first device region for forming a first plurality...
29	7569893	Method of fabricating semiconductor device and semiconductor device fabricated thereby A method includes preparing a semiconductor substrate having a cell region, a core NMOS region, and a core PMOS region; defining a cell active region, an NMOS active region, and a PMOS active...
30	7569892	Method and structure for forming self-aligned, dual stress liner for CMOS devices A method for forming a self-aligned, dual stress liner for a CMOS device includes forming a first type stress layer over a first polarity type device and a second polarity type device, and forming...
31	7569891	Semiconductor device with reduced contact resistance and method for manufacturing the same It is made possible to reduce the contact resistance of the source and drain in an n-type MISFET. A semiconductor device includes: a source and drain regions provided in a p-type semiconductor...
32	7569890	Manufacturing method of CMOS type semiconductor device, and CMOS type semiconductor device The manufacturing method of the CMOS type semiconductor device which can suppress the boron penetration from the gate electrode of the pMOS transistors to the semiconductor substrate in the case...
33	7569889	Memory integrated circuit, in particular an SRAM memory integrated circuit, and corresponding fabrication process A RAM memory integrated circuit, in particular a SRAM memory integrated circuit, includes a matrix of memory cells that are arranged between two bit lines via two access transistors. The bit lines...
34	7569888	Semiconductor device with close stress liner film and method of manufacturing the same Aspects of the present disclosure are generally directed to FETs with stress liners that are closer than typical stressed FETs, as well as methods for manufacturing the same. FETE channel sidewall...
35	7569466	Dual metal gate self-aligned integration A semiconductor structure including at least one n-type field effect transistor (nFET) and at least one p-type field effect transistor (pFET) that both include a metal gate having nFET behavior and...
36	7566936	Complementary MIS device A CMOS device includes a p-channel MOS transistor and an n-channel MOS transistor having a structure formed on a (100) surface of a silicon substrate and having a different crystal surface, a...
37	7564102	Semiconductor device and its manufacturing method A method for manufacturing a semiconductor device wherein both the threshold voltages of an N-type MISFET and a P-type MISFET are low, device can be easily manufactured at a lower cost and a higher...
38	7564073	CMOS and HCMOS semiconductor integrated circuit A semiconductor integrated circuit fabrication method according to this invention includes: a step of forming a pair of first device forming regions and a pair of second device forming regions in a...
39	7560781	Semiconductor device and fabrication method thereof A semiconductor device includes a first insulating layer and a second insulating layer in a trench. The first insulating layer insulates two MOSFETs from each other, and the second insulating layer...
40	7560780	Active region spacer for semiconductor devices and method to form the same A semiconductor device and method for its fabrication are described. An active region spacer may be formed on a top surface of an isolation region and adjacent to a sidewall of an active region. In...
41	7560779	Method for forming a mixed voltage circuit having complementary devices A mixed voltage circuit is formed by providing a substrate ( 12 ) having a first region ( 20 ) for forming a first device ( 106 ), a second region ( 22 ) for forming a second device ( 108 )...
42	7557414	Semiconductor device and method for manufacturing the same In a semiconductor device having a first MIS transistor on a semiconductor substrate, the first MIS transistor includes a p-type semiconductor layer, a first gate insulating film, a first gate...
43	7547947	SRAM cell Disclosed is an SRAM cell on an SOI, bulk or HOT wafer with two pass-gate n-FETs, two pull-up p-FETs and two pull-down n-FETs and the associated methods of making the SRAM cell. The pass-gate FETs...
44	7545005	Semiconductor device capable of avoiding latchup breakdown resulting from negative variation of floating offset voltage A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper...
45	7545004	Method and structure for forming strained devices A method for manufacturing a device includes mapping extreme vertical boundary conditions of a mask layer based on vertical edges of a deposited first layer and a second layer. The mask layer is...
46	7545002	Low noise and high performance LSI device, layout and manufacturing method In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular...
47	7544555	Method of manufacturing semiconductor device A dummy oxide film having a film thickness that is the same as that of a gate oxide film of a high voltage transistor is formed on a gate electrode of a transistor, and the dummy oxide film and the...
48	7541650	Gate electrode structures Gate electrode structures used in field effect transistors and integrated circuits and methods of manufacture are disclosed. Improved work function and threshold modulation are provided by the...
49	7535064	Semiconductor device having a fin and method of manufacturing the same A semiconductor device includes a Fin, a source region and a drain region, a first extension region, a second extension region and a channel region. The Fin is formed on a major surface of a...
50	7534676	Method of forming enhanced device via transverse stress In the present invention, a PMOS device comprises a channel region formed in {100} silicon with first and second source/drain region disposed on either side of the channel region. The channel...

Matches 1 - 50 out of 1116

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