Matches 401 - 450 out of 1121 < 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 >
Match Document Document Title
6605846 Shallow junction formation  
A method of forming junctions in a semiconductor substrate, where a gate dielectric layer is grown on the semiconductor substrate, a gate electrode layer is deposited on the gate dielectric layer,...
6603178 Semiconductor integrated circuit device and method of manufacture thereof  
Disclosed is a semiconductor integrated circuit device (e.g., an SRAM) having memory cells each of a flip-flop circuit constituted by a pair of drive MISFETs and a pair of load MISFETs, the MISFETs...
6603179 Semiconductor apparatus including CMOS circuits and method for fabricating the same  
6600205 Method for making low voltage transistors with increased breakdown voltage to substrate having three different MOS transistors  
A high-breakdown voltage transistor ( 30; 30′ ) is disclosed. The transistor ( 30; 30′ ) is formed into a well arrangement in which a shallow, heavily doped, well ( 44 ) is disposed at least...
6597041 Semiconductor static random access memory device  
A memory cell of an SRAM has a full CMOS cell structure having successively aligned three wells of different conductivity types, and includes first and second contact holes extending from positions...
6593628 Semiconductor device and method of manufacturing same  
The invention relates to an essentially discrete semiconductor device comprising a semiconductor body ( 10 ) having a first, preferably bipolar, transistor (T 1 ) with a first region ( 1 ) forming...
6590265 Semiconductor device with sidewall spacers having minimized area contacts  
A contact opening ( 940 ) is provided in a dielectric layer ( 720 ) overlaying a gate electrode ( 840 ). The contact opening and gate electrode are of substantially the same width, thus allowing...
6576962 CMOS SRAM cell with prescribed power-on data state  
A CMOS SRAM cell with prescribed power-on data state having first and second cross-coupled inverters each defined by serially connected complementary MOS transistors (T 1 /T 2 ; T 3 /T 4 ) serially...
6570227 High-performance high-density CMOS SRAM cell  
A high-performance high-density CMOS SRAM cell (MC) having first and second cross-coupled inverters each defined by serially connected complementary MOS transistors (TA/TC; TB/TD) serially...
6566720 Base cell layout permitting rapid layout with minimum clock line capacitance on CMOS standard-cell and gate-array integrated circuits  
A base cell for a gate array or standard cell integrated circuit design has N and P wells organized in checkerboard fashion, each well containing several P and N devices respectively. A first of...
6566719 Semiconductor integrated circuit  
The method of manufacturing a semiconductor integrated circuit device, which has an n-channel MIS transistor and a p-channel MIS transistor formed in the same semiconductor substrate, comprises ion...
6563178 Semiconductor device and method for fabricating the device  
A first gate electrode for an n-channel MOSFET includes first and second metal films and a low-resistivity metal film. The first metal film has been deposited on a first gate insulating film and is...
6559821 Matrix substrate and liquid crystal display as well as projector using the same  
A liquid crystal display comprising one or more than one shift registers is characterized in that the timing of turning off the input gate of the inverter connected to the gate of the pMOS...
6555879 SOI device with metal source/drain and method of fabrication  
A MOSFET and method of fabrication. The MOSFET includes a metal containing source and a metal containing drain; a semiconductor body having a thickness of less than about 15 nm disposed between the...
6548842 Field-effect transistor for alleviating short-channel effects  
An IGFET ( 40 or 42 ) has a channel zone ( 64 or 84 ) situated in body material ( 50 ). Short-channel threshold voltage roll-off and punchthrough are alleviated by arranging for the net dopant...
6545324 Dual metal gate transistors for CMOS process  
A process for forming a first transistor of a first conductivity type and a second transistor of a second conductivity type in a semiconductor substrate is disclosed. The substrate has a first well...
6545323 Semiconductor memory device including a pair of MOS transistors forming a detection circuit  
A semiconductor device includes a semiconductor layer used as a substrate formed on an insulating film, a plurality of MOS transistors arranged on the semiconductor layer and each having a gate, a...
6541821 SOI device with source/drain extensions and adjacent shallow pockets  
A Silicon-on-Insulator (SOI) transistor includes an intrinsic body layer that is fully depleted when in a conductive state. The transistor includes a shallow pocket of dopants adjacent to each of...
6538278 CMOS integrated circuit having PMOS and NMOS devices with different gate dielectric layers  
A CMOS integrated circuit having a PMOS and NMOS device with different gate dielectric layers. According to the present invention, an NMOS transistor is formed on a p-type conductivity region of a...
6534805 SRAM cell design  
An embodiment of a memory cell includes a series of four substantially oblong parallel active regions, arranged side-by-side such that the inner active regions of the series include source/drain...
6534864 Semiconductor memory device and method of fabricating the same  
A semiconductor memory device (SRAM) comprises memory cells, each of which includes two load transistors, two driver transistors and two transfer transistors. The SRAM cell includes a semiconductor...
6534835 Damascene structure with low dielectric constant insulating layers  
A damascene structure with a plurality of low dielectric constant insulating layers acting as etch stops is disclosed. The selected low dielectric constant materials have similar methods of...
6531746 Semiconductor device with high-speed switching circuit implemented by MIS transistors and process for fabrication thereof  
An n-channel type MIS field effect transistor is fabricated on a p-type well defined in a standard p-type silicon substrate, and is expected to respond to a high-frequency signal, wherein a...
6528852 Double gated electronic device and method of forming the same  
In a field effect type device having a thin film-like active layer, there is provided a thin film-like semiconductor device including a top side gate electrode on the active layer and a bottom side...
6528833 CMOS active pixel for improving sensitivity  
A CMOS active pixel of increased sensitivity includes a floating diffusion layer, a photo-diode, a reset circuit and an output circuit The floating diffusion layer is of a first dopant type and...
6528842 Electronically erasable memory cell using CMOS technology  
An Electrically Erasable Programmable Read Only Memory (EEPROM) cell uses a single standard NMOS (or PMOS) transistor with its gate connected to a Metal-Insulator-Metal, or Poly-Insulator-Poly...
6525380 CMOS with a fixed charge in the gate dielectric  
A semiconductor device—which includes surface-type n-channel and p-channel single gate transistors by formation of fixed charges within a gate oxide film—and a manufacturing method therefor. A...
6524902 Method of manufacturing CMOS semiconductor device  
In a CMOS semiconductor device having a substrate, a gate insulating layer formed on the substrate, at least one first polysilicon gate formed over the substrate in at least one PMOS transistor...
6521953 Semiconductor CMOS structures with an undoped region  
A method of implanting dopants into a semiconductor structure is described wherein a lateral periphery of a photoresist mask is shifted after implanting a first dopant and prior to implanting a...
6521960 Column transistor for semiconductor devices  
A column transistor of a sense amplifier includes an orthogonal matrix of a plurality of sets of four active regions, bit lines and local data lines running perpendicular to each other, with each...
6514830 Method of manufacturing high voltage transistor with modified field implant mask  
A method of manufacturing a high voltage transistor exhibiting high gated diode breakdown voltage, low leakage and low body effect while avoiding an excessive number of costly masking steps. A high...
6512273 Method and structure for improving hot carrier immunity for devices with very shallow junctions  
An integrated circuit CMOS structure and method for forming the structure provides gate sidewall spacers which are independently optimized for the n-channel and p-channel devices to improve...
6512274 CMOS-process compatible, tunable NDR (negative differential resistance) device and method of operating same  
An n-channel metal-insulator-semiconductor field-effect transistor (MISFET) that exhibits negative differential resistance in its output characteristic (drain current as a function of drain...
6512272 Increased gate to body coupling and application to dram and dynamic circuits  
An FET and DRAM using a plurality of such FETs wherein each transistor has a body region of a first conductivity type including a relatively high V T region and relatively low V T region, the...
6509609 Grooved channel schottky MOSFET  
A grooved channel Schottky contacted MOSFET has asymmetric source and drain regions. The MOSFET includes an undoped silicon substrate with a background doping concentration of less than about 10 17...
6504218 Asymmetrical N-channel and P-channel devices  
An asymmetrical N-channel IGFET and an asymmetrical P-channel IGFET are disclosed. One or both IGFETs include a lightly doped drain region, heavily doped source and drain regions, and an...
6503787 Device and method for forming semiconductor interconnections in an integrated circuit substrate  
The present invention provides a semiconductor device, formed on a semiconductor wafer, comprising a tub, first and second active areas, and an interconnect. In one aspect of the present invention,...
6495408 Local interconnection process for preventing dopant cross diffusion in shared gate electrodes  
Disclosed is a process of electrically coupling the gate electrodes of an N-type transistor and a P-type transistor without causing substantial cross diffusion of P-type dopants into the N-type...
6492671 CMOS process  
A high-voltage MOS transistor is produced in a low-voltage CMOS process without adding extra process steps for producing the high-voltage MOS For. The high-voltage MOS transistor is to be used as...
6492688 Dual work function CMOS device  
A method for forming a CMOS device. The method includes forming a gate oxide over a surface of a semiconductor substrate. A first doped layer is formed over the gate oxide. The first doped layer is...
6492674 Semiconductor device having an improved plug structure and method of manufacturing the same  
A conductive plug is formed in an interlayer insulation film and on an isolating layer which isolates semiconductor elements on a semiconductor substrate. The conductive plug electrically connects...
6486516 Semiconductor device and a method of producing the same  
A semiconductor device and a method of producing the semiconductor device, fabricated by forming a memory device and a logic device on a single semiconductor substrate, are provided. A side wall (...
6483171 Vertical sub-micron CMOS transistors on (110), (111), (311), (511), and higher order surfaces of bulk, SOI and thin film structures and method of forming same  
A method for forming NMOS and PMOS transistors that includes cutting a substrate along a higher order orientation and fabricating deep sub-micron NMOS and PMOS transistors on the vertical surfaces...
6477694 Method for designing a power supply decoupling circuit  
A design support system 100 according to the present invention comprises: an LSI library 10 , in which rated characteristics of various LSIs are stored by an LSI library preparation unit 70 ; a...
6476430 Integrated circuit  
In transistors with sub-micron channels, short-channel effects, such as a lowering of the threshold voltage, are usually suppressed by means of a halo (or pocket) implant in the source/drain...
6476451 Buried guard rings for CMOS device  
A twin-well CMOS integrated circuit device includes an n-well region and a p-well region. Each of the n-well and p-well region includes spaced-apart regions which serve as drain and source regions,...
6472767 Static random access memory (SRAM)  
A semiconductor body having a pair of vertical, double-gated CMOS transistors. An insulating layer extending horizontally beneath the surface of the semiconductor body such insulating layer being...
6472712 Semiconductor device with reduced transistor leakage current  
A semiconductor device improved to suppress a leakage current of a transistor is provided. A gate electrode is disposed on a semiconductor substrate. A pair of p type source/drain layers are...
6468860 Integrated circuit capable of operating at two different power supply voltages  
A method for manufacturing an integrated circuit having high voltage transistors and low voltage transistors is disclosed. First, lightly doped drains are formed in both high voltage transistors...
6469351 Electrostatic breakdown prevention circuit for semiconductor device  
A Vss-side off transistor is often used in an electrostatic breakdown prevention circuit having an NMOS transistor. In such a circuit, the state of connection of the transistor ensures that...
Matches 401 - 450 out of 1121 < 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 >