Matches 351 - 400 out of 1121 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >
Match Document Document Title
6768179 CMOS of semiconductor device and method for manufacturing the same  
CMOS device arrangements have a surface channel, and a method for manufacturing the same by forming a multi-layer that includes a first metal layer, a polysilicon layer and a second metal layer...
6762465 BiCMOS inverter  
A semiconductor device 1000 may include first and second switch elements 1000 A and 1000 B formed in first and second element forming regions 16 a and 16 b of a SOI layer 10 a ,...
6759717 CMOS integrated circuit device with LDD n-channel transistor and non-LDD p-channel transistor  
A method of fabricating an integrated circuit having an n-channel and a p-channel transistor is provided. The method includes forming LDD regions for the n-channel transistors self-aligned to the...
6753581 Method of isolating a SRAM cell  
A static random access memory cell comprising a first invertor including a first p-channel pullup transistor, and a first n-channel pulldown transistor in series with the first p-channel pullup...
6750532 CMOS semiconductor device and method of manufacturing the same  
In a CMOS semiconductor device having a substrate, a gate insulating layer formed on the substrate, at least one first polysilicon gate formed over the substrate in at least one PMOS transistor...
6750515 SCR devices in silicon-on-insulator CMOS process for on-chip ESD protection  
A silicon-on-isolator CMOS integrated circuit device includes a semiconductor substrate, an isolation layer formed over the semiconductor substrate, an n-type MOS transistor having a gate, a drain...
6747320 Semiconductor device with DRAM inside  
A semiconductor device is provided in which the difference in characteristics between a pair of sense amplifier transistors of a DRAM is suppressed, whereby the sensitivity of a sense amplifier is...
6747319 Semiconductor device and method of fabricating the same  
A semiconductor device including multiple high-voltage drive transistors in its output section is improved in electrostatic withstand voltage by connecting electrostatic protection transistors in...
6744101 Non-uniform gate/dielectric field effect transistor  
A field effect transistor (FET) structure, and method for making the same, which further suppresses short-channel effects based on variations within the gate dielectric itself. The FET structure...
6744102 MOS transistors with nitrogen in the gate oxide of the p-channel transistor  
In accordance with an aspect of the invention, a semiconductor processing method of forming field effect transistors includes forming a first gate dielectric layer over a first area configured for...
6734506 Semiconductor device including a plurality of kinds of MOS transistors having different gate widths and method of manufacturing the same  
A semiconductor device, comprises a first MOS transistor including a gate electrode having a gate width Le and a first gate post oxide film formed on the circumferential side wall of the gate...
6730952 Semiconductor device including ion implantion compensation region in cell array region  
A first mask which is formed which exposes a cell array region and a peripheral circuit region of a semiconductor substrate. The cell array region and the peripheral circuit region are of a same...
6730973 Semiconductor device  
A first pattern forming a memory cell is provided on a memory cell region, and a second pattern consisting of a film containing nitrogen atoms is provided on the first pattern. A third pattern...
6727546 Self-aligned triple gate silicon-on-insulator (SOI) device  
A self-aligned transistor including a first silicon portion on an isolation layer, the silicon portion having formed therein a source region and a drain region separated by a channel region. The...
6720627 Semiconductor device having junction depths for reducing short channel effect  
A semiconductor device and a fabrication method thereof are disclosed. A silicon nitride film is formed over a silicon semiconductor substrate. Impurity ions are then implanted into desired areas...
6713823 Conductive routings in integrated circuits  
An integrated circuit structure with a first layer that has a first conductive area and a second conductive area that is electrically isolated from the first area, and a second layer that has a...
6713819 SOI MOSFET having amorphized source drain and method of fabrication  
An integrated circuit formed in semiconductor-on-insulator format. The integrated circuit includes a layer of semiconductor material disposed on an insulating layer, where the insulating layer...
6711727 Method and arrangement for layout and manufacture of gridless nonManhattan semiconductor integrated circuits  
The present invention introduces several methods for implementing integrated circuits that use gridless non Manhattan routing to connect the integrated circuit components. In one embodiment, the...
6710412 Static semiconductor memory device  
An SRAM includes first and second access PMOS transistors in an N well region; first and second driver NMOS transistors in a P well region; a word line; and first and second bit lines. Active...
6707116 Integrated circuit and manufacturing method therefor  
An integrated circuit is manufactured by providing a P − or P −− type semiconductor substrate with a resistivity of 10 to 1000 Ω·cm, disposing a CMOS on top of the semiconductor...
6703655 Ferroelectric memory transistor  
A ferroelectric memory transistor includes a substrate having active regions therein; a gate stack, including: a high-k insulator element, including a high-k cup and a high-k cap; a ferroelectric...
6696735 Semiconductor device and method for fabricating the same  
A semiconductor device according to one aspect of the present invention, is a semiconductor device comprising: a first MOS field effect transistor of an n-type including a first oxynitride film as...
6696328 CMOS gate electrode using selective growth and a fabrication method thereof  
A CMOS gate electrode formed using a selective growth method and a fabrication method thereof, wherein, in the CMOS gate electrode, a first gate pattern of polysilicon germanium (poly-SiGe) is...
6693001 Process for producing semiconductor integrated circuit device  
A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETs by silicidizing a Co film deposited on a...
6690075 Semiconductor device with channel having plural impurity regions  
In a CMOS circuit, impurity regions are formed in the channel forming region of each of an n-channel and p-channel transistors alone the channel direction. The intervals between the impurity...
6686631 Negative differential resistance (NDR) device and method of operating same  
An n-channel metal-insulator-semiconductor field-effect transistor (MISFET) that exhibits negative differential resistance in its output characteristic (drain current as a function of drain...
6683352 Semiconductor device structure  
A metal oxide semiconductor field effect transistor structure is disclosed. A p-shape gate, disposed over a semiconductor substrate. A gate dielectric layer is disposed in between the p-shape gate...
6674105 Semiconductor memory device and method of forming the same  
In accordance with the present invention, the gate length and the gate insulation film thickness are different between the p-channel MOS field effect transistors serving as the driver gates and the...
6670680 Semiconductor device comprising a dual gate CMOS  
A dual gate type CMOS device according to the present invention includes a silicon substrate having a trench in the main surface and a gate electrode including a polysilicon film and a tungsten...
6671147 Double-triggered electrostatic discharge protection circuit  
A double-triggered electrostatic discharge (ESD) protection circuit for coupling with a first voltage source and a second voltage source. The circuit includes a diode series and a transistor. The...
6670681 Semiconductor structures  
A method of implanting dopants into a semiconductor structure wherein a lateral periphery of a photoresist mask is shifted after implanting a first dopant and prior to implanting a second dopant....
6667519 Mixed technology microcircuits  
A mixed technology microcircuit including a first circuit fabricated on a first layer with a first technology and a second circuit fabricated on a second layer with a second technology. In the...
6664601 Method of orperating a dual mode FET & logic circuit having negative differential resistance mode  
A process for operating a dual mode FET and a logic circuit to include a negative differential resistance (NDR) characteristic is disclosed. In a FET embodiment, an NDR characteristic is...
6664608 Back-biased MOS device  
A plurality of p-wells and n-wells are formed in a front side of a bulk material, and a plurality of n layers and p layers are alternately formed within the bulk material between a back side of the...
6661063 Semiconductor integrated circuit device  
Disclosed is a semiconductor integrated circuit device (e.g., an SRAM) having memory cells each of a flip-flop circuit constituted by a pair of drive MISFETs and a pair of load MISFETs, the MISFETs...
6661055 Transistor in semiconductor devices  
The present invention relates to a transistor in a semiconductor device and method of manufacturing the same. According to the present invention, the transistor has an auxiliary electrode to which...
6661061 Integrated circuit with differing gate oxide thickness  
A semiconductor process for producing two gate oxide thicknesses within an integrated circuit in which a semiconductor substrate having a first region and a second region is provided. The first...
6657257 Insulated gate field effect transistor and semiconductor integrated circuit  
According to the present invention, there is provided an N-type insulated gate field effect transistor using an SOI substrate of which Si layer as a device formation area is N-type. The SOI...
6653679 Reduced 1/f noise in MOSFETs  
An improved gate structure for a MOSFET device exhibits a reduced level of 1/f noise or “flicker noise”, while maintaining the control of boron penetration into the substrate of the MOSFET...
6649985 Insulated-gate semiconductor device for a rectifier  
An insulated-gate semiconductor device comprises a source region (S) formed on a predetermined semiconductor substrate such as a ball semiconductor, a drain region (D) formed on the semiconductor...
6649948 Solid-state image sensor of a MOS structure  
In a MOS type solid-state image sensor having an image pickup area formed at a semiconductor substrate and comprising a two-dimensional array of row and column unit cells including a photoelectric...
6639287 Semiconductor integrated circuit device  
A semiconductor device has a depletion type MIS transistor, a transistor forming a masked ROM, and a submicron CMOS integrated on a single or common semiconductor substrate, while minimizing the...
6635935 Semiconductor device cell having regularly sized and arranged features  
In a semiconductor device, first gate electrodes contributing to transistor operations and second gate electrodes not contributing to the transistor operations each have the same gate length, share...
6630717 CMOS semiconductor circuit with reverse bias applied for reduced power consumption  
An integrated CMOS semiconductor circuit comprises: an internal circuit composed of CMOS transistors including P3- and N-channel transistors each having a gate electrode and source/drain regions...
6630716 Disposable spacer  
A disposable spacer for use in a semiconductor device fabrication process is formed of a germanium-silicon alloy. The germanium-silicon alloy may include a first portion (x) of germanium and a...
6624459 Silicon on insulator field effect transistors having shared body contact  
Silicon on insulator (SOI) field effect transistors (FET) with a shared body contact, a SRAM cell and array including the SOI FETs and the method of forming the SOI FETs. The SRAM cell has a hybrid...
6624493 Biasing, operation and parasitic current limitation in single device equivalent to CMOS, and other semiconductor systems  
Disclosed are semiconductor devices including at least one junction which is rectifying whether the semiconductor is caused to be N or P-type, by the presence of applied gate voltage field induced...
6621125 Buried channel device structure  
A buried channel device structure for an electrostatic discharge protection circuit capable of minimizing the effect on the electrostatic discharge protection circuit due to current flowing close...
6613626 Method of forming CMOS transistor having a deep sub-micron mid-gap metal gate  
A CMOS transistor is formed on a single crystal silicon substrate. Active regions are formed on the substrate, including an nMOST active region and a pMOST active region. An epitaxial layer of...
6611030 Cmosfet with conductive, grounded backside connected to the wiring layer through a hole that separates the Mosfets  
An improved semiconductor device, and a corresponding fabrication method thereof, are provided that include a ground region defined in a semiconductor substrate. A hole is formed using a known...
Matches 351 - 400 out of 1121 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >