Patents in Class 257/369

Matches 51 - 100 out of 1122

Match	Document	Document Title
51	7545002	Low noise and high performance LSI device, layout and manufacturing method In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular...
52	7545005	Semiconductor device capable of avoiding latchup breakdown resulting from negative variation of floating offset voltage A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper...
53	7544555	Method of manufacturing semiconductor device A dummy oxide film having a film thickness that is the same as that of a gate oxide film of a high voltage transistor is formed on a gate electrode of a transistor, and the dummy oxide film and the...
54	7541650	Gate electrode structures Gate electrode structures used in field effect transistors and integrated circuits and methods of manufacture are disclosed. Improved work function and threshold modulation are provided by the...
55	7535064	Semiconductor device having a fin and method of manufacturing the same A semiconductor device includes a Fin, a source region and a drain region, a first extension region, a second extension region and a channel region. The Fin is formed on a major surface of a...
56	7534676	Method of forming enhanced device via transverse stress In the present invention, a PMOS device comprises a channel region formed in {100} silicon with first and second source/drain region disposed on either side of the channel region. The channel...
57	7531881	Semiconductor devices having transistors with different gate structures and methods of fabricating the same A semiconductor device has two transistors of different structure from each other. One of transistors is P-type and the other is N-type. One of the transistors includes a gate structure in which a...
58	7531880	Semiconductor device and manufacturing method thereof A device includes a semiconductor layer on an insulating layer; a gate insulator on the semiconductor layer; a comb-shaped gate electrode on the gate insulator, including a base portion extending...
59	7528450	Semiconductor device having NMOSFET and PMOSFET and manufacturing method therefor A element isolation insulating film is formed around the device regions in the silicon substrate. The device regions are formed an n-type diffusion layer region, a p-type diffusion layer region, a...
60	7525162	Orientation-optimized PFETS in CMOS devices employing dual stress liners A PFET is provided on a silicon layer having a (110) surface orientation and located in a substrate. A compressive stress liner disposed on the gate and source/drain regions of the PFET generates a...
61	7525161	Strained MOS devices using source/drain epitaxy NMOS and PMOS device structures with separately strained channel regions and methods of their fabrication are disclosed. The source and the drain of the NMOS device is epitaxially grown of a...
62	7525160	Multigate device with recessed strain regions Embodiments of the invention provide a device with a multiple gates. Stress material within recesses of a device body metal gate may cause a stress in channel regions of the device, thereby...
63	7521762	Semiconductor integrated circuit device operating with low power consumption Transistors having large gate tunnel barriers are used as transistors to be on in a standby state, MIS transistors having thin gate insulating films are used as transistors to be off in the standby...
64	7517779	Recessed drain extensions in transistor device A method of forming an integrated circuit transistor ( 50 ). The method provides a first semiconductor region ( 52 ) and forms ( 110 ) a gate structure ( 54 x ) in a fixed position relative to the...
65	7518512	Transponder device A transponder device comprises an integrated CMOS circuit with a semiconductor substrate. A first rectifying diode (DS) is formed by the substrate diode of the CMOS circuit. A first MOS transistor...
66	7518193	SRAM array and analog FET with dual-strain layers comprising relaxed regions Disclosed is a semiconductor structure and associated method of performing the structure with good performance and stability trade-offs for digital circuits and SRAM cells and/or analog FETs on the...
67	7514752	Reduction of short-circuiting between contacts at or near a tensile-compressive boundary Methods and apparatus are described that reduce the possibility that unintended subway short-circuits will occur between contacts of different potentials along the boundary between tensile and...
68	7514753	Semiconductor device A semiconductor device comprises n-type and p-type semiconductor devices formed on the substrate, the n-type device including an n-channel region formed on the substrate, n-type source and drain...
69	7511338	Semiconductor device and manufacturing method of the same An object of the present invention is to simplify manufacturing process of an n channel MIS transistor and a p channel MIS transistor with gate electrodes formed of a metal material. For its...
70	7511360	Semiconductor device having stressors and method for forming N channel and P channel transistors are enhanced by applying stressor layers of tensile and compressive, respectively, over them. A previously unknown problem was discovered concerning the two...
71	7511989	Memory cells in double-gate CMOS technology provided with transistors with two independent gates This invention relates to an improved microelectronic RAM memory device, provided with 4T or 6T cells made using the double gate technology and each associated with two word lines.
72	7504696	CMOS with dual metal gate Embodiments herein present a structure and method to make a CMOS with dual metal gates. Specifically, the CMOS comprises a first gate comprising a first metal and a second gate comprising a second...
73	7506146	Fast and compact circuit for bus inversion A bussed system with a fast and compact majority voter in the circuitry responsible for the bus inversion decision. The majority voter is implemented in analog circuitry having two branches. One...
74	7504677	Multi-gate enhancement mode RF switch and bias arrangement Methods and apparatus are provided for RF switches ( 100, 200 ). In a preferred embodiment, the apparatus comprises one or more multi-gate n-channel enhancement mode FET transistors ( 50, 112, 114...
75	7501686	Semiconductor device and method for manufacturing the same A semiconductor device is disclosed that includes a semiconductor substrate, a device region disposed at a predetermined location of the semiconductor substrate, and a shallow trench isolation...
76	7498657	Vertical resistors and band-gap voltage reference circuits A vertical resistor. A substrate includes a trench filled by an isolation layer. A first doped-type region and a second doped-type region are formed on both sides of the trench. The first...
77	7491973	Semiconductor LSI circuit having a NAND logic gate with a highly integrated and microscopic structure Basic logic gates are formed in a small area, and a highly integrated and microscopic structure is provided. In an nMOSFET and a pMOSFET, gate electrodes are formed facing each other and...
78	7492015	Complementary carbon nanotube triple gate technology Disclosed is a CNT technology that overcomes the intrinsic ambipolar properties of CNTFETs. One embodiment of the invention provides either a stable p-type CNTFET or a stable n-type CNTFET. Another...
79	7492016	Protection against charging damage in hybrid orientation transistors A chip includes a CMOS structure having a bulk device disposed in a first region of a semiconductor substrate in conductive communication with an underlying bulk region of the substrate, the first...
80	7492014	Semiconductor device A semiconductor device wherein the same metal gate material is used for both an n-channel CMOS transistor and a p-channel CMOS transistor and a manufacturing method therefor are disclosed. The...
81	7486541	Resistive cell structure for reducing soft error rate A memory cell for reducing soft error rate and the method for forming same are disclosed. The memory cell comprises a first bit line signal (BL), a second bit line signal complementary to the first...
82	7485932	ACCUFET with Schottky source contact An accumulation mode FET (ACCUFET) which includes an insulated gate, an adjacently disposed insulated source field electrode, and a source contact that makes Schottky contact with the base region...
83	7482671	MOS semiconductor device isolated by a device isolation film A MOS semiconductor device isolated by a trench device isolation region includes a p-channel MOS field effect transistor having a source/drain region with a length in the channel direction that is...
84	7479674	Field effect transistor An field effect transistor includes a first semiconductor region, a gate electrode insulatively disposed over the first semiconductor region, source and drain electrodes between which the first...
85	7476578	Process for finFET spacer formation A process for finFET spacer formation generally includes depositing, in order, a conformal liner material, a conformal spacer material, and a conformal capping material onto the finFET structure;...
86	7473640	Reactive gate electrode conductive barrier A method, and corresponding transistor structure are provided for protecting the gate electrode from an underlying gate insulator. The method comprises: forming a gate insulator overlying a channel...
87	7473985	Hybrid oriented substrates and crystal imprinting methods for forming such hybrid oriented substrates A semiconductor structure with an insulating layer on a silicon substrate, a plurality of electrically-isolated silicon-on-insulator (SOI) regions separated from the substrate by the insulating...
88	7465970	Common pass gate layout of a D flip flop A semiconductor layout includes a p substrate, a first semiconductor cell formed over the p substrate, and a second semiconductor cell formed over the p substrate adjacent to the first...
89	7462914	Semiconductor circuit device and simulation method of the same A first PMIS transistor includes a first active region which is formed on a semiconductor substrate and a first gate electrode which is formed on the first active region and which is connected at...
90	7462915	Method and apparatus for increase strain effect in a transistor channel A semiconductor device having a transistor channel with an enhanced stress is provided. To achieve the enhanced stress transistor channel, a nitride film is preferentially formed on the device...
91	7459752	Ultra thin body fully-depleted SOI MOSFETs Ultra thin body fully-depleted silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect-transistors (MOSFETs) in which the SOI thickness changes with gate-length variations thereby...
92	7456448	Semiconductor device and method for producing the same A semiconductor device, including a first MIS-type transistor formed in a first region of a semiconductor region, the first region being of a first conductivity type, the first MIS-type transistor...
93	7456450	CMOS devices with hybrid channel orientations and method for fabricating the same The present invention relates to a semiconductor substrate comprising at least first and second device regions, wherein the first device region comprises a first recess having interior surfaces...
94	7453120	Semiconductor structure A method for fabricating a semiconductor structure is described. A substrate is provided, having thereon a gate structure and a spacer on the sidewall of the gate structure and having therein an...
95	7449753	Write margin improvement for SRAM cells with SiGe stressors A semiconductor structure including SRAM cells with improved write margins and a method for forming the same are provided. The semiconductor structure comprises a substrate including a core circuit...
96	7445981	Method for forming a dual metal gate structure A method includes forming a first gate dielectric layer over a semiconductor layer having a first and a second well region, forming a first metal gate electrode layer over the first gate...
97	7442601	Stress enhanced CMOS circuits and methods for their fabrication A stress enhanced CMOS circuit and methods for its fabrication are provided. One fabrication method comprises the steps of forming an NMOS transistor and a PMOS transistor adjacent the NMOS...
98	7442995	Semiconductor device and method of manufacturing the same Each of channel regions 2 a and 3 b is covered by a gate electrode 6 via a gate insulation film 5 and side wall spacers 9 from its top face to both side faces along an x-direction. In...
99	7439588	Tri-gate integration with embedded floating body memory cell using a high-K dual metal gate Dual-gate memory cells and tri-gate CMOS devices are integrated on a common substrate. A plurality of silicon bodies are formed from a monocrystalline silicon on the substrate to define a plurality...
100	7439140	Formation of standard voltage threshold and low voltage threshold MOSFET devices Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked,...

Matches 51 - 100 out of 1122

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