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7012308 Diode  
A diode which eliminates generation of local avalanche breakdown phenomenon when static surges in the backward direction are applied and withstands electrostatic breakdown. A P-type impurity...
7012304 Diode and transistor design for high speed I/O  
An integrated circuit including a performance circuit occupying a first area of an integrated circuit substrate and a protection circuit coupled to the performance circuit and occupying a second...
7012307 Output buffer with good ESD protection  
An output buffer with a pull down circuit. The pull down circuit is coupled between a second power line and a pad, and has a resistor, a diode and an electrostatic discharge protection component....
7005708 Minimum-dimension, fully-silicided MOS driver and ESD protection design for optimized inter-finger coupling  
An electrostatic discharge (ESD) MOS transistor including a plurality of interleaved fingers, where the MOS transistor is formed in an I/O periphery of and integrated circuit (IC) for providing...
7002219 Electrical fuse for integrated circuits  
An electrically programmable fuse includes a metal-oxide-semiconductor (MOS) programmable transistor that is gate-source coupled by a resistive element. The resistive element can comprise a...
7002218 Low capacitance ESD-protection structure under a bond pad  
An ESD-protection structure is located substantially under an integrated circuit bond pad. This ESD-protection structure is formed as a low capacitance structure by inserting a forward diode...
6979908 Input/output architecture for integrated circuits with efficient positioning of integrated circuit elements  
A described embodiment of the present invention includes an integrated circuit having a plurality of I/O modules. The I/O modules include a bond pad formed on a substrate. The I/O modules also...
6979869 Substrate-biased I/O and power ESD protection circuits in deep-submicron twin-well process  
A semiconductor device which includes a P-well which is underneath NMOS fingers. The device includes an N-well ring which is configured so that the inner P-well underneath the NMOS fingers is...
6977421 Semiconductor constructions  
The invention includes a DRAM array having a structure therein which includes a first material separated from a second material by an intervening insulative material. The first material is doped...
6969904 Trimming pattern  
There is provided a trimming pattern enabling trimming to be implemented with ease and time required for trimming to be shortened without causing damage to internal elements. The invention...
6967378 Semiconductor integrated circuit device configured to prevent the generation of a reverse current in a MOS transistor  
A semiconductor integrated circuit device has a MOS transistor M2 including a parasitic diode Dx2 for preventing a reverse current due to a parasitic diode Dx1 of a MOS transistor M1. The...
6963111 Efficient pMOS ESD protection circuit  
A pMOS transistor (601) is located in an n-well (602) and has at least one gate (603). Transistor (601) is connected between power pad Vdd or I/O pad (604) and ground potential Vss (605). Gate...
6960784 Charging sensor method and apparatus  
A charging sensor is provided to detect charging signal during the manufacturing process of integrated circuits and various semiconductor devices. In one embodiment, the charging sensor includes a...
6953971 Device for adjusting circuits before encapsulation  
A device for adjusting an integrated circuit before encapsulation includes a first MOS transistor having a gate and a source connected together, and a body connected to a voltage reference. A...
6952027 Semiconductor integrated circuit device and electronic card using the same  
A semiconductor integrated circuit device includes a semiconductor region of a first conductivity type. A first insulated-gate field effect transistor having a source/drain region of a second...
6952037 Electrostatic discharge semiconductor protection circuit of reduced area  
A semiconductor device includes a substrate, a well region formed in the substrate, a field effect transistor formed in the well region, and a diffused region, formed across the well region and...
6946690 High holding voltage ESD protection structure and method  
The holding voltage (the minimum voltage required for operation) of a LVTSCR-like device is increased to a value that is greater than a dc bias on a to-be-protected node. The holding voltage is...
6943412 Semiconductor integrated circuit  
A semiconductor integrated circuit is provided, which has an improved withstanding voltage for electrostatic breakdown at the time of electrostatic discharge by the charged device model, in the...
6940104 Cascaded diode structure with deep N-well and method for making the same  
A cascaded diode structure with a deep N-well for effectively reducing the leakage current of the P-type substrate by floating the base of a parasitic transistor in the cascaded diode structure....
6940137 Semiconductor device having an angled compensation implant and method of manufacture therefor  
The present invention provides a semiconductor device 200 having an angled compensation implant, a method of manufacture therefore and a method of manufacturing an integrated circuit including the...
6940128 Semiconductor device for power MOS transistor module  
A first transistor has a first main electrode region which is formed so that these are subdivided into a plurality of first isolated island region. A second transistor has its first main electrode...
6940131 MOS ESD CDM clamp with integral substrate injection guardring and method for fabrication  
The present invention includes a MOS device (100) that has a P-type substrate (102) and an N-type drain region (104) formed within the substrate (102). An annular N-type source region (106)...
6936896 Semiconductor apparatus  
A low voltage thyristor is disclosed that can be used to provide protection during electrostatic discharge event. The thyristor is connected between voltage reference nodes having a common...
6933567 Substrate pump ESD protection for silicon-on-insulator technologies  
An electrostatic discharge (ESD) protection device formed in the semiconductor layer of a semiconductor-on-insulator device, wherein the semiconductor layer has first and second wells. A discharge...
6927457 Circuit structure for connecting bonding pad and ESD protection circuit  
A circuit structure for connecting a bonding pad with an electrostatic discharge protection circuit. The circuit structure includes a plurality of conductive layers, a first plurality of first...
6924532 Field-effect power transistor  
The present invention provides a field-effect power transistor having a first semiconductor region (10) with first channels (20) having a large ratio of a channel width (w) to a channel length (l)...
6919588 High-voltage silicon controlled rectifier structure with improved punch through resistance  
When a high-voltage, such as from an ESD pulse, is placed across a silicon controlled rectifier, which includes an NPN transistor and a PNP transistor that is connected to the NPN transistor, the...
6919602 Gate-coupled MOSFET ESD protection circuit  
A gate-coupled MOSFET ESD protection circuit. The circuit has a gate-node potential controlled by an inverter and a timing control circuit. Unlike current-shunting ESD clamping devices that turn...
6914305 Circuits and methods for electrostatic discharge protection in integrated circuits  
An output circuit of an integrated circuit device includes first and second MOS transistors including respective spaced apart pairs of source and drain regions in a substrate, arranged such that...
6911700 Semiconductor integrated circuit device including digital and analog circuits comprising electrostatic destruction protection circuits  
A semiconductor integrated circuit including a digital circuit and an analog circuit which are integrated on a single semiconductor chip comprises a first electrostatic destruction protection...
6882011 ESD protection device having reduced trigger voltage  
An ESD protection device having reduced trigger voltage is disclosed. A first MOS transistor includes a first gate, a first heavily doped region at one side of the first gate, and a second heavily...
6873015 Semiconductor constructions comprising three-dimensional thin film transistor devices and resistors  
The invention includes semiconductor constructions having a thin film stacked resistor in electrical connection with a source/drain region of a transistor device. The resistor includes first and...
6870229 Ultra-low power basic blocks and their uses  
The present invention relates to an ultra-low power (ULP) MOS diode. The diode has a first and a second terminal. It comprises an n-MOS transistor having a channel, a first N+ doped diffusion...
6864537 Thick gate oxide transistor and electrostatic discharge protection utilizing thick gate oxide transistors  
An electrostatic discharge (ESD) protection circuit includes a transistor with a gate electrode isolated from the semiconductor substrate by a thick oxide, a collector clamp coupled with a pad and...
6858901 ESD protection circuit with high substrate-triggering efficiency  
An ESD protection circuit with high substrate-triggering efficiency. The circuit comprises a multi-finger-type device having a plurality of finger gates below which a parasitic BJT is formed, a...
6858900 ESD protection devices and methods to reduce trigger voltage  
ESD protection devices and methods of forming them are provided in this invention. By employing the thin gate oxide fabricated by a dual gate oxide process and breakdown-enhanced layers, ESD...
6858902 Efficient ESD protection with application for low capacitance I/O pads  
A semiconductor device for ESD protection of an input/output pad (301) of an integrated circuit built in a substrate of a first conductivity type comprising a multi-finger MOS transistor (304),...
6855964 Triggering of an ESD NMOS through the use of an N-type buried layer  
An ESD NMOS structure with an odd number of N-type structures built into a P-type well. Buried N-type structures are positioned between the N-type structures. The center N-type structure and each...
6847083 Semiconductor device, electro-optic device, and electronic instrument  
This invention provides a semiconductor device that does not cause a defect at an intersection of wirings even when a surge voltage enters from a signal input terminal, an electro-optic device...
6844573 Structure for minimizing hot spots in SOI device  
In a high power input/output SOI semiconductor structure, the transistors thereof are laid out in a manner so that the high current density transistors, subject to the greatest heat buildup, are...
6838734 ESD implantation in deep-submicron CMOS technology for high-voltage-tolerant applications  
High-voltage-tolerant ESD protection devices (ESDPD) for deep-submicron CMOS process were activated between LDD implanting and forming sidewall spacers. ESD-Implant (ESDI) regions are located at...
6838700 Active matrix substrate  
An active matrix substrate includes a row and column array of active elements. Each element is associated with a TFT having a gate electrode connected to a corresponding row conductor and source...
6833590 Semiconductor device  
An NMOS transistor circuit has a surge protection circuit connected in parallel with the NMOS transistor. A resistor is connected between a back gate of the NMOS transistor and ground. As a...
6833568 Geometry-controllable design blocks of MOS transistors for improved ESD protection  
An MOS transistor in the surface of a semiconductor substrate (180) of a first conductivity type, which has a grid of isolations (171) in the surface, each grid unit surrounding a rectangular...
6822296 Complementary metal oxide semiconductor structure for battery protection circuit and battery protection circuit having the same  
A complementary metal-oxide semiconductor (CMOS) structure for a battery protection circuit and a battery protection circuit therewith. A tri-well technique or a buried layer technique is used for...
6818955 Electrostatic discharge protection  
An electrostatic discharge device may provide better protection of an integrated circuit by more uniform breakdown of a plurality of finger regions. The plurality of finger regions may extend...
6815776 Multi-finger type electrostatic discharge protection circuit  
A multi-finger type electrostatic discharge protection circuit is disclosed. In an NMOS type ESD protection circuit, a pair of gates are formed in parallel with each other in one of multiple...
6815775 ESD protection design with turn-on restraining method and structures  
The present invention is directed to an electrostatic discharge (ESD) device with an improved ESD robustness for protecting output buffers in I/O cell libraries. The ESD device according to the...
6803632 Semiconductor circuit having an input protection circuit  
A semiconductor circuit has an output circuit, an input circuit and an input protection circuit. The output circuit is connected to a first power supplying terminal and a reference terminal for...
6791122 Silicon controlled rectifier electrostatic discharge protection device with external on-chip triggering and compact internal dimensions for fast triggering  
A silicon controlled rectifier electrostatic discharge protection circuit with external on-chip triggering and compact internal dimensions for fast triggering. The ESD protection circuit includes...