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6590264 |
Hybrid diodes with excellent ESD protection capacity
Hybrid diodes with excellent ESD protection capacity. Each hybrid diode has two diodes: one is a poly-bounded diode formed as a junction between a substrate and a diffusion region thereon, the...
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6590262 |
High voltage ESD protection device with very low snapback voltage
A device layout is disclosed for an ESD device for protecting NMOS high voltage transistors where the SCR protection device and the two NMOS transistors are integrated. The two NMOS transistors...
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6590241 |
MOS transistors with improved gate dielectrics
The specification describes silicon MOS devices with gate dielectrics having the composition Ta 1−x Al x O y , where x is 0.03-0.7 and y is 1.5-3, Ta 1−x Si x O y , where x is 0.05-0.15, and y...
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6589823 |
Silicon-on-insulator (SOI)electrostatic discharge (ESD) protection device with backside contact plug
An electrostatic discharge (ESD) protection device for a silicon-on-insulator (SOI) integrated circuit having a silicon substrate with a buried oxide layer disposed thereon and an active layer...
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6583476 |
Electrostatic discharge protection for integrated semiconductor devices using channel stop field plates
A semiconductor structure which protects against damages to an integrated circuit caused by electrostatic discharge (ESD) at a power supply pin includes a channel stop field plate coupled between a...
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6580131 |
LDMOS device with double N-layering and process for its manufacture
The tradeoff between breakdown voltage and on-resistance for LDMOS devices has been improved by having two epitaxial N−regions instead of the single epitaxial N−region that is used by devices...
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6580184 |
Electrostatic discharge (ESD) protection circuit of silicon-controlled rectifier (SCR) structure operable at a low trigger voltage
An ESD protection circuit having silicon-controlled rectifier structure, includes a PNP transistor and an NPN transistor. A switch circuit is connected between a ground voltage terminal and a well...
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6576934 |
Embedded SCR protection device for output and input pad
An embedded SCR in conjunction with a Gated-NMOS is created for protecting a chip input or output pad from ESD, by inserting a p+ diffusion and the n-well in the drain side and a part of the drain...
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6577481 |
Cascoded NPN electrostatic discharge protection circuit
The electrostatic discharge protection circuit includes: at least two bipolar transistors Q 1 -Qn coupled in series; a top one Qn of the at least two bipolar transistors coupled to a protected node...
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6576958 |
ESD protection networks with NMOS-bound or PMOS-bound diode structures in a shallow-trench-isolation (STI) CMOS process
Novel PMOS-bound and NMOS-bound diodes for ESD protection, together with their application circuits, are disclosed in this invention. The PMOS-bound (or NMOS bound) diode has a PMOS (or an NMOS)...
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6570225 |
Method for improved electrostatic discharge protection
A method includes introducing into an integrated circuit a device comprising a transistor including a drain of a first conductivity type and a first concentration in a well of a first conductivity...
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6566717 |
Integrated circuit with silicided ESD protection transistors
An electrostatic discharge (ESD) protection circuit for protecting an internal device from an ESD is disclosed. The ESD protection circuit includes an NMOS transistor connected to a ground voltage...
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6566238 |
Metal wire fuse structure with cavity
An integrated circuit has primary devices and redundant devices being selective substituted for the primary devices through at least one fuse. The fuse includes a first layer having at least one...
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6566715 |
Substrate-triggered technique for on-chip ESD protection circuit
In this invention, a novel substrate-triggered technique is proposed to effectively improve the electrostatic discharge (ESD) robustness of integrated circuit (IC) products. The ESD protection...
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6566684 |
Active matrix circuit having a TFT with pixel electrode as auxiliary capacitor
There is provided a combination of doping process and use of side walls which allows the source and drain of a thin film transistor of an active matrix circuit to be doped with only one of N-type...
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6559508 |
ESD protection device for open drain I/O pad in integrated circuits with merged layout structure
An open drain driver circuit and a Vss to Vdd FET with a merged layout structure are formed to provide a short path for an ESD current from an associated pad and either Vss or Vdd. The short path...
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6560081 |
Electrostatic discharge (ESD) protection circuit
An ESD protection circuit that can be easily configured to provide ESD event protection against a range of ESD event voltages. The circuit is also compatible with high frequency ICs. The ESD...
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6559507 |
Compact ballasting region design for snapback N-MOS ESD protection structure using multiple local N&plus region blocking
In a n+ snapback device, saturation current is limited by using one or more NLDD current blocking regions. This limits the snapback saturation current, while avoiding current stratification by...
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6559503 |
Transistor with ESD protection
The transistor has source and drain diffusion regions between which a gate electrode is disposed. In order to increase the sheet resistance of the source and/or drain diffusion regions, a plurality...
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6555878 |
Umos-like gate-controlled thyristor structure for ESD protection
Described is a MOS gate-controlled SCR (UGSCR) structure with a U-shaped gate (UMOS) for an ESD protection circuit in an IC device which is compatible with shallow trench isolation (STI) and...
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6555877 |
NMOSFET with negative voltage capability formed in P-type substrate and method of making the same
A semiconductor device ( 10,50 ) is disclosed which can accommodate a negative voltage on its source using a P-type substrate ( 12 ) which is connected to ground potential. A first embodiment...
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6552372 |
Integrated circuit having improved ESD protection
An MOS integrated circuit, such as an input-output buffer, exhibits improved resistance to damage from electrostatic discharge (ESD) by balancing the ESD current flow through active and inactive...
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6552397 |
Charge pump device formed on silicon-on-insulator and operation method
A charge pump formed in a silicon-on-insulator (SOI) substrate is disclosed. The charge pump comprises a SOI layer formed on a substrate. Formed in the silicon of the SOI is a first p-body and a...
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6548868 |
ESD protection clamp with internal zener diode
In a ESD protection clamp, breakdown and triggering voltage of the structure are reduced by introducing an internal zener diode structure that has a lower avalanche breakdown than the p-n junction...
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6548869 |
Voltage limiting protection for high frequency power device
An RF power device comprising a power transistor fabricated in a first semiconductor chip and a MOSCAP type structure fabricated in a second semiconductor chip. A voltage limiting device is...
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6545321 |
ESD protection circuit for a semiconductor integrated circuit
When an ESD surge positive against a ground terminal is loaded on the input/output pad, a breakdown current of the n-channel MOS transitor flows via forward-biased diodes consist of a p+ diffusion...
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6545322 |
Semiconductor protection device
There is provided a semiconductor integrated circuit device with high electrostatic resistance. A semiconductor device is provided with a transistor for input-output protection having a desired...
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6541820 |
Low voltage planar power MOSFET with serpentine gate pattern
A three mask process is described for a low voltage, low on-resistance power MOSFET. A serpentine gate divides a non-epi silicon die into laterally separated drain and source regions with a very...
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6541801 |
Triac with a holding voltage that is greater than the dc bias voltages that are on the to-be-protected nodes
The holding voltage (the minimum voltage required for operation) of a triac is increased to a value that is greater than a dc bias on to-be-protected nodes. The holding voltage is increased by...
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6541824 |
Modified source side inserted anti-type diffusion ESD protection device
An ESD protection circuit that will prevent internal circuits of an integrated circuit is formed on a semiconductor substrate to prevent damage during extreme voltage levels from an ESD voltage...
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6542346 |
High-voltage tolerance input buffer and ESD protection circuit
A high-voltage tolerance input buffer and a high-voltage ESD protection circuit connected to a pad of an integrated circuit for preventing rapid gate oxide aging. The high-voltage tolerance input...
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6538288 |
ESD protection device with island-like distributed p&plus diffusion regions
An electrostatic discharge (ESD) protection structure for an integrated circuit constructed on a substrate of a first type is provided to includes a plurality of island-like distributed diffusion...
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6538266 |
Protection device with a silicon-controlled rectifier
A semiconductor device for lowering a triggering voltage includes a semiconductor substrate with a first conductivity; a semiconductor region formed in the substrate having a second conductivity; a...
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6538290 |
Static protection device
A static protection device protects an internal circuit of a semiconductor device from surge voltages. An emitter terminal of the PNP transistor is connected to the input/output terminal, a...
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6538304 |
Corner bonding to lead frame
A lead frame for an integrated circuit includes a ground for the integrated circuit to ground the integrated circuit, the lead frame having at least one corner connected to the ground; and a...
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6534833 |
Semiconductor device with protection circuitry and method
The invention comprises a semiconductor device with protection circuitry and a method of protecting an integrated circuit from electrostatic discharge. One aspect of the invention is a...
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6534834 |
Polysilicon bounded snapback device
A snapback device functions as a semiconductor protection circuit to prevent damage to integrated circuits due to events such as electrostatic discharge and the like. The snapback device is capable...
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6531744 |
Integrated circuit provided with overvoltage protection and method for manufacture thereof
The invention concerns an integrated circuit, including a substrate (SBSTR) with sub-circuits provided with a number of terminals, including a substrate terminal or earthing point (GND), a V cc ...
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6529035 |
Arrangement for improving the ESD protection in a CMOS buffer
An arrangement for improving the ESD protection in a CMOS buffer includes a plurality of PMOS transistors ( 31 to 37 ) and a plurality of NMOS transistors ( 41-47 ) which are connected in series...
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6528836 |
Photomask ESD protection and an anti-ESD pod with such protection
An active anti-ESD pod for transporting photomask (reticle) comprises six body portions delimiting the container, an electrically conducting plate on the top portion, and an electrically conducting...
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6524941 |
Sub-minimum wiring structure
A semiconductor wiring structure positioned between plurality conductors, comprisies spacers positioned on adjacent ones of the conductors and at least one wiring element positioned between the...
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6521951 |
Semiconductor circuit device with improved surge resistance
Inter power supply surge voltage transmitting diode element is formed by a buried layer formed in a semiconductor substrate, a well region formed on the buried layer with its bottom portion being...
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6521946 |
Electrostatic discharge resistant extended drain metal oxide semiconductor transistor
A semiconductor device comprising a first transistor ( 40 ) and a second transistor ( 100 ), both formed in a semiconductor substrate ( 50 ). The first transistor comprises a gate conductor ( 56 )...
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6515337 |
Input protection circuit connected to projection circuit power source potential line
An input protection circuit capable of precisely bypassing a surge current to a power source terminal and protecting the gate of a protective transistor from an electrostatic surge. The input...
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6509617 |
Semiconductor device and fabrication method thereof
A semiconductor device according to the present invention includes a first guard ring having conductivity of one of N and P types and a second guard ring formed adjacent to the first guard ring and...
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6509585 |
Electrostatic discharge protective device incorporating silicon controlled rectifier devices
An SCR cell structure provides a plurality of divided p+ and n+ blocks, and varies the spacing, sizes and locations of these divided p+ and n+ blocks to minimize latchup caused by non-ESD events....
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6504212 |
Method and apparatus for enhanced SOI passgate operations
A method and apparatus are provided for implementing enhanced silicon-on-insulator (SOI) passgate operations. The apparatus for implementing enhanced silicon-on-insulator (SOI) passgate operations...
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6504216 |
Electrostatic discharge protective circuit
An electrostatic discharge protective circuit. The electrostatic discharge protective circuit includes a gate electrode. A drain is formed at one side of the gate electrode. A source is formed at...
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6501136 |
High-speed MOSFET structure for ESD protection
A multi-gate-finger MOSFET structure positions the gate element over a channel between drain and source diffusion regions, such that the entire structure is within the active region in a substrate....
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6501137 |
Electrostatic discharge protection circuit triggered by PNP bipolar action
An electrostatic discharge protection circuit, comprising a semiconductor-controlled rectifier and a PMOS device. The semiconductor-controlled rectifier, coupled between two nodes, has an N-type...
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