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7622774 Method of manufacturing semiconductor device and semiconductor device  
Disclosed is a semiconductor device of n-type MOSFET structure, which comprises a semiconductor substrate having a device isolation region, diffusion regions formed in the semiconductor substrate,...
7598570 Semiconductor device, SRAM and manufacturing method of semiconductor device  
A semiconductor device according to the present invention is provided with an SOI substrate, an active region, a first insulating film (complete separation insulating film), a second insulating...
7592671 Strained silicon-on-insulator by anodization of a buried p+ silicon germanium layer  
A cost efficient and manufacturable method of fabricating strained semiconductor-on-insulator (SSOI) substrates is provided that avoids wafer bonding. The method includes growing various epitaxial...
7582934 Isolation spacer for thin SOI devices  
A semiconductor device comprises a semiconductor mesa overlying a dielectric layer, a gate stack formed overlying the semiconductor mesa, and an isolation spacer formed surrounding the...
7579655 Transistor structure having interconnect to side of diffusion and related method  
A transistor structure is disclosed including at least one transistor including a diffusion and an interconnect electrically connected to a side of the diffusion and a conductor in electrical...
7579636 MIS-type field-effect transistor  
A strained Si layer 2 is epitaxially grown on a base SiGe layer 1 , and a gate insulating film 3 a and a gate electrode 4 a are formed. An impurity is then ion-implanted (FIG. 2 A) into the...
7566630 Buried silicon dioxide / silicon nitride bi-layer insulators and methods of fabricating the same  
Embodiments of the present invention relate to the fabrication of a buried bi-layer insulator of silicon oxide and silicon nitride in a microelectronic substrate, and to the buried silicon...
7544999 SOI semiconductor device having enhanced, self-aligned dielectric regions in the bulk silicon substrate  
In one illustrative embodiment, the method comprises forming a gate electrode above an SOI substrate comprised of a bulk substrate, a buried insulation layer and an active layer, the gate electrode...
7525155 High voltage transistor structure for semiconductor device  
A high voltage MOS transistor has a thermally-driven-in first doped region and a second doped region that form a double diffused drain structure. Boundaries of the first doped region are graded. A...
7521760 Integrated circuit chip with FETs having mixed body thickness and method of manufacture thereof  
An Integrated Circuit (IC) chip that may be a bulk CMOS IC chip with silicon on insulator (SOI) Field Effect Transistors (FETs) and method of making the chip. The IC chip includes areas with...
7521776 Soft error reduction of CMOS circuits on substrates with hybrid crystal orientation using buried recombination centers  
Novel semiconductor structures and methods are disclosed for forming a buried recombination layer underneath the bulk portion of a hybrid orientation technology by implanting at least one...
7514732 Image pickup apparatus and image pickup system having plural semiconductor regions of a same conductivity type, with one of the semiconductor regions having a higher impurity concentration than and providing a potential to another of the semiconductor regions  
A solid-state image pickup apparatus with little or no difference in the dark currents between adjacent photoelectric conversion elements and providing a high sensitivity and a low dark current...
7507988 Semiconductor heterostructure including a substantially relaxed, low defect density SiGe layer  
A heterostructure is provided which includes a substantially relaxed SiGe layer present atop an insulating region that is located on a substrate. The substantially relaxed SiGe layer has a...
7501674 Semiconductor device having fin transistor and planar transistor and associated methods of manufacture  
Disclosed is a fin transistor and a planar transistor and a method of forming the same. The fin transistor and the planar transistor are formed to have gate electrodes with similar thicknesses by...
7498636 Semiconductor device and method of manufacturing the same  
Variations in characteristics of transistors and a deterioration of a gate oxide film are reduced in a WP step. A method of manufacturing a semiconductor device of the present invention includes...
7492009 Semiconductor device having silicon on insulator structure and method of fabricating the same  
A semiconductor device capable of making an effective use of a support substrate as interconnect is proposed. The semiconductor device (chip 4 ) of the present invention has a first Si substrate ...
7491964 Nitridation of STI fill oxide to prevent the loss of STI fill oxide during manufacturing process  
A method and structure for an improved shallow trench isolation (STI) structure for a semiconductor device. The STI structure incorporates an oxynitride top layer of the STI fill. Optionally, the...
7470951 Hybrid-FET and its application as SRAM  
A semiconductor device ( 51 ) is provided herein. The semiconductor device comprises (a) a substrate ( 57 ), a semiconductor layer ( 53 ) disposed on said substrate and comprising a horizontal...
7456476 Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication  
A nonplanar semiconductor device and its method of fabrication is described. The nonplanar semiconductor device includes a semiconductor body having a top surface opposite a bottom surface formed...
7456474 Semiconductor device having insulating film  
Channel doping is an effective method for controlling V th , but if V th shifts to the order of −4 to −3 V when forming circuits such as a CMOS circuit formed from both an n-channel TFT and a...
7453122 SOI MOSFET device with reduced polysilicon loading on active area  
Silicon-on-insulator (SOI) devices with reduced polysilicon loading on an active area uses at least one dielectric layer resistant to silicidation to separate at least one body contact region from...
7442958 Thin film semiconductor device  
A thin film semiconductor device is provided which includes an insulating substrate, a Si thin film formed over the insulating substrate, and a transistor with the Si thin film as a channel...
7439585 Silicon-on-insulator device  
A Silicon on Insulator (SOI) device is disclosed wherein an extension of P-type doping ( 303 ) is implanted between the buried oxide layer of the device and the SOI layer. The extension is of a...
7432552 Body biasing structure of SOI  
A body biasing structure of devices connected in series on an SOI substrate is provided. According to some embodiments, the shallow junction of common source/drain regions enables all devices to...
7423313 NAND-type semiconductor storage device and method for manufacturing same  
According to this invention, there is provided a NAND-type semiconductor storage device including a semiconductor substrate, a semiconductor layer formed on the semiconductor substrate, a buried...
7423321 Double gate MOSFET device  
A method of fabricating a double gate MOSFET device is provided. The present invention overetches a silicon layer overlying a buried oxide layer using a hard mask of cap oxide on the silicon layer...
7423324 Double-gate MOS transistor, double-gate CMOS transistor, and method for manufacturing the same  
In a double-gate MOS transistor, a substrate, an insulating layer, and a semiconductor layer are formed or laminated in that order, an opening extending to the insulating layer is formed in the...
7420249 Semiconductor device formed in semiconductor layer arranged on substrate with one of insulating film and cavity interposed between the substrate and the semiconductor layer  
A semiconductor device including a first semiconductor layer formed on a semiconductor substrate, a second semiconductor layer surrounding the first semiconductor layer, the second semiconductor...
7414289 SOI Device with charging protection and methods of making same  
The present invention is directed to an SOI device with charging protection and methods of making the same. In one illustrative embodiment, a device is formed on an SOI substrate including a bulk...
7394130 Transistor and method for manufacturing the same  
In a process for manufacturing a thin film transistor having a semiconductor layer constituting source and drain regions and a channel forming region, by the semiconductor layer being made thinner...
7382024 Low threshold voltage PMOS apparatus and method of fabricating the same  
A P-type metal oxide semiconductor (PMOS) device can include an N-well that does not extend completely throughout the active region of the PMOS device. For example, the PMOS device can be...
RE40339 Silicon-on-insulator chip having an isolation barrier for reliability  
An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above...
7372106 Semiconductor device and method for manufacturing semiconductor device  
A semiconductor device comprising electric field relieving regions 8 a and 8 b for alleviating the electric fields between a source layer 6 a and body-source connection layers 7 a and 7 b ...
7358569 Semiconductor device with semiconductor layer having various thickness  
An SOI layer is provided in a buried oxide film and a source and a drain are provided on the upper surface of the SOI layer so that they are kept from contact with the buried oxide film. A...
7358571 Isolation spacer for thin SOI devices  
A semiconductor device comprises a semiconductor mesa overlying a dielectric layer, a gate stack formed overlying the semiconductor mesa, and an isolation spacer formed surrounding the...
7355247 Silicon on diamond-like carbon devices  
Embodiments of the invention provide substrate with an insulator layer on the substrate. The insulator layer may include diamond-like carbon. A device, such a tri-gate transistor may be formed on...
7339237 Connection, configuration, and production of a buried semiconductor layer  
A power transistor has a semiconductor volume including a plurality of transistor cells connected in parallel, a laterally oriented, highly conductive semiconductor layer buried below the...
7335950 Semiconductor device and method of making thereof  
To provide a thin film transistor having a low OFF characteristic and to provide P-channel type and N-channel type thin film transistors where a difference in characteristics of the P-channel type...
7332777 STI liner for SOI structure  
In a method of manufacturing a semiconductor device, an initial structure is provided. The initial structure includes a substrate, a patterned silicon layer, and a covering layer. The substrate has...
7326975 Buried channel type transistor having a trench gate and method of manufacturing the same  
In a method of manufacturing a buried channel type transistor, a trench is formed at a surface portion of a substrate. A first and a second threshold voltage control regions are formed at portions...
7323716 Manufacturing method of thin film transistor substrate  
This invention provides a manufacturing method for fabricating on the same substrate both high voltage thin film transistors suitable for driving liquid crystal and low voltage drive high...
7323753 MOS transistor circuit and voltage-boosting booster circuit  
To an output of an NMOS having one end connected to a power source, a capacitor and a PMOS are connected. A capacitor is connected to the output of the PMOS. The NMOS and the PMOS are turned on...
7306998 Formation of abrupt junctions in devices by using silicide growth dopant snowplow effect  
A method of forming an abrupt junction device with a semiconductor substrate is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed on the gate dielectric. A...
7301219 Electrically erasable programmable read only memory (EEPROM) cell and method for making the same  
An asymmetrically doped memory cell has first and second N+ doped junctions on a P substrate. A composite charge trapping layer is disposed over the P substrate and between the first and the second...
7271447 Semiconductor device  
A semiconductor substrate includes a first semiconductor layer that is formed on a semiconductor base substrate, a second semiconductor layer that is formed on the first semiconductor layer and...
7271456 Semiconductor devices including stress inducing layers  
A semiconductor device may include a substrate and a fin shaped semiconductor region on the substrate. The fin shaped semiconductor region may include a channel region and first and second junction...
7271442 Transistor structure having stressed regions of opposite types underlying channel and source/drain regions  
An integrated circuit and method of fabrication are provided in which the integrated circuit includes a field effect transistor (FET) having a channel region and source and drain regions adjacent...
7262468 Method and system for reducing charge damage in silicon-on-insulator technology  
According to one embodiment of the invention, a silicon-on-insulator device includes an insulative layer formed overlying a substrate and a source and drain region formed overlying the insulative...
7256456 SOI substrate and semiconductor integrated circuit device  
A semiconductor IC device includes a base substrate comprising P − -type silicon, a first P + -type silicon layer is provided on the base substrate, and an N + -type silicon layer and a second P...
7253520 CSP semiconductor device having signal and radiation bump groups  
A semiconductor device comprises a semiconductor chip which has a first surface, a pad which is formed directly on the first surface, an oxide film which is formed on the first surface, an...
Matches 1 - 50 out of 369 1 2 3 4 5 6 7 8 >