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7417285 Semiconductor device having a trench capacitor and a MOSFET connected by a diffusion layer and manufacturing method thereof  
A semiconductor device comprises a semiconductor substrate having a first conductivity type, a trench capacitor, provided in the semiconductor substrate, having a charge storage region, a gate...
7339235 Semiconductor device having SOI structure and manufacturing method thereof  
A fine semiconductor device having a short channel length while suppressing a short channel effect. Linearly patterned or dot-patterned impurity regions 104 are formed in a channel forming region...
7332770 Semiconductor device  
A semiconductor device of this invention is a vertical power MOSFET having a plurality of first trenches where a trench gate is formed. It has a first column region of a second conductivity type...
7329922 Dual-gate metal-oxide semiconductor device  
An MOS device includes first and second source/drain regions of a first conductivity type formed in a semiconductor layer of a second conductivity type proximate an upper surface of the...
7323753 MOS transistor circuit and voltage-boosting booster circuit  
To an output of an NMOS having one end connected to a power source, a capacitor and a PMOS are connected. A capacitor is connected to the output of the PMOS. The NMOS and the PMOS are turned on...
7312500 Manufacturing method of semiconductor device suppressing short-channel effect  
An ideal step-profile in a channel region is realized easily and reliably, whereby suppression of the short-channel effect and prevention of mobility degradation are achieved together. A silicon...
7288817 Reverse metal process for creating a metal silicide transistor gate structure  
The present invention teaches a method of forming a MOSFET transistor having a silicide gate which is not subject to problems produced by etching a metal containing layer when forming the gate...
7276773 Power semiconductor device  
A power semiconductor device includes second semiconductor layers of a first conductivity type and third semiconductor layers of a second conductivity type alternately disposed on a first...
7265416 High breakdown voltage low on-resistance lateral DMOS transistor  
In accordance with the present invention, a metal oxide semiconductor (MOS) transistor has a substrate of a first conductivity type. A drift region of a second conductivity type extends over the...
7160783 MOS transistor and method of manufacturing the same  
A metal oxide semiconductor (MOS) transistor and a method of manufacturing the same are disclosed. An example MOS transistor includes a semiconductor substrate of a first conductivity type where an...
7078769 Nonvolatile memory and manufacturing method thereof  
Memory elements, switching elements, and peripheral circuits to constitute a nonvolatile memory are integrally formed on a substrate by using TFTs. Since semiconductor active layers of memory...
7067880 Transistor gate structure  
The present invention teaches a method of forming a MOSFET transistor having a silicide gate which is not subject to problems produced by etching a metal containing layer when forming the gate...
7057238 Semiconductor device and method for fabricating the same  
A semiconductor device and a method for fabricating the same are provided. The provided semiconductor device includes a field oxide layer formed in a semiconductor substrate to define an active...
7057236 Semiconductor device and manufacturing method thereof  
After forming a gate electrode on a semiconductor substrate, ion implantation is performed on the semiconductor substrate by using the gate electrode as a mask to form low concentration impurity...
7045876 Amorphizing ion implant method for forming polysilicon emitter bipolar transistor  
A method for fabricating a polysilicon emitter bipolar transistor employs a pair of ion implant methods. A first of the ion implant methods implants a portion of an intrinsic base region interposed...
7042051 Semiconductor device including impurity layer having a plurality of impurity peaks formed beneath the channel region  
Provided is a manufacturing method of a semiconductor device which comprises forming, all over the surface of a substrate below the channel region of a MISFET, a p type impurity layer having a...
7038270 Nonvolatile memory device with a non-planar gate-insulating layer and method of fabricating the same  
A non-volatile memory device with a non-planar gate insulating layer and a method of fabricating the same are provided. The device includes a tunnel insulating pattern, a charge storage layer, an...
7019379 Semiconductor device comprising voltage regulator element  
A semiconductor device includes a heavily doped layer 25 of p-type formed in the surface of an n-type well 21, an intermediately doped layer 26 of p-type formed to adjoin and surround the...
7015546 Deterministically doped field-effect devices and methods of making same  
Deterministically doped field-effect devices and methods of making same. One or more dopant atoms, also referred to as impurities or impurity atoms, are arranged in the channel region of a device...
7009265 Low capacitance FET for operation at subthreshold voltages  
A field effect transistor (FET) has underlap regions adjacent to the channel doping region. The underlap regions have very low dopant concentrations of less than 1×10 17 /cc or 5×10 16 /cc and so...
7009258 Method of building a CMOS structure on thin SOI with source/drain electrodes formed by in situ doped selective amorphous silicon  
The present invention provides improved controllability of the lateral etch encroachment of silicon under the spacer, in light of the fact that the exemplary method, in accordance with the present...
7009248 Semiconductor device with asymmetric pocket implants  
A semiconductor device ( 1 ) has a source ( 2 ) a gate ( 3 ) and a drain ( 4 ), a single deep-pocket ion implant ( 8 ) in a source-drain depletion region, and a single shallow-pocket ion implant (...
6995428 High voltage LDMOS transistor having an isolated structure  
A high voltage LDMOS transistor according to the present invention includes a P-field and divided P-fields in an extended drain region of a N-well. The P-field and divided P-fields form...
6995427 Semiconductor structure for providing strained crystalline layer on insulator and method for fabricating same  
A semiconductor structure having a high-strained crystalline layer with a low crystal defect density and a method for fabricating such a semiconductor structure are disclosed. The structure...
6982456 Nonvolatile semiconductor memory device and method for fabricating the same  
A nonvolatile semiconductor memory device according to the present invention has a control gate electrode which is formed on the upper stage of a stepped portion formed in the principal surface of...
6979885 Devices with patterned wells and method for forming same  
In a semiconductor substrate with a top surface, a PN junction between a first region of one conductivity type formed by masked diffusion into a semiconductor from the surface and a second region...
6977418 Low resistance semiconductor process and structures  
A process for forming a semiconductor device comprises the steps of providing a semiconductor substrate assembly comprising a semiconductor wafer having an active area formed therein, a plurality...
6974999 Semiconductor device and method of manufacturing the same  
It is an object to suppress a change in a characteristic of a semiconductor device with a removal of a hard mask while making the most of an advantage of a gate electrode formed by using the hard...
6974998 Field effect transistor with corner diffusions for reduced leakage  
The present invention includes an advanced MOSFET design and manufacturing approach that allow further increase in IC packing density by appropriately addressing the increased leakage problems...
6965151 Device including a resistive path to introduce an equivalent RC circuit  
Structures for providing devices that include resistive paths specifically designed to provide a predetermined resistance between the bulk material of the device and a well tie contact. By...
6956262 Charge trapping pull up element  
A charge trapping semiconductor device is particularly suited as a replacement for conventional pull-up and load elements such as NDR diodes, passive resistors, and conventional FETs. The device...
6933564 Semiconductor integrated circuit device and method of manufacturing the same  
An impurity ion of a polarity opposite to that of an impurity ion forming an n-type diffusion layer is implanted into a lower portion of the n-type diffusion region in a region, in which n-channel...
6917077 Protection diode for improved ruggedness of a radio frequency power transistor and self-defining method to manufacture such protection diode  
A semiconductor arrangement including: a substrate having a substrate layer ( 13 ) with an upper and lower surface, the substrate layer ( 13 ) being of a first conductivity type; a first...
6897526 Semiconductor device and process for producing the same  
To provide a semiconductor device that can effectively suppress the short channel effect without deterioration of carrier migration, an impurity ion is added from a direction of the < 110 >...
6881630 Methods for fabricating field effect transistors having elevated source/drain regions  
Field effect transistors (FETs) include an integrated circuit substrate having a surface, and a gate on the surface. A pair of recessed regions in the substrate are located beneath the surface....
6873011 High voltage and low on-resistance LDMOS transistor having equalized capacitance  
A high voltage LDMOS transistor according to the present invention includes P-field blocks in the extended drain region of a N-well. The P-field blocks form the junction-fields in the N-well for...
6873008 Asymmetrical devices for short gate length performance with disposable sidewall  
An asymmetrical channel implant from source to drain improves short channel characteristics. The implant provides a relatively high V T net dopant adjacent to the source region and a relatively...
6870233 Multi-bit ROM cell with bi-directional read and a method for making thereof  
A multi-bit Read Only Memory (ROM) cell has a semiconductor substrate of a first conductivity type with a first concentration. A first and second regions of a second conductivity type spaced apart...
6870224 MOS transistor apparatus and method of manufacturing same  
When polycrystalline silicon germanium film is used for gate electrodes in a MOS transistor apparatus, there have been problems of reduced reliability in the gate insulating film, due to stress in...
6867458 Semiconductor device and method for fabricating the same  
Provided is a semiconductor device having a source region formed of a semiconductor, a drain region formed of a semiconductor of the same conductive type as that of the source region, a channel...
6867085 Insulated gate semiconductor device and method of manufacturing the same  
Dot-pattern-like impurity regions are artificially and locally formed in a channel forming region. The impurity regions restrain the expansion of a drain side depletion layer toward the channel...
6864533 MOS field effect transistor with reduced on-resistance  
A semiconductor substrate includes a first principal plane and a second principal plane opposite this first principal plane. A first semiconductor region is formed on the first principal plane of...
6861707 Negative differential resistance (NDR) memory cell with reduced soft error rate  
An active negative differential resistance element (an NDR FET) and a memory device (such as an SRAM) using such elements is disclosed Soft error rate (SER) performance for NDR FETs and such memory...
6853035 Negative differential resistance (NDR) memory device with reduced soft error rate  
An active negative differential resistance element (an NDR FET) and a memory device (such as an SRAW using such elements is disclosed Soft error rate (SER) performance for NDR FETs and such memory...
6835980 Semiconductor device with novel film composition  
A method of depositing a thin film on a substrate in a semiconductor device using Atomic Layer Deposition (ALD) process parameters exposes the substrate to at least one adherent material in a...
6825530 Zero Threshold Voltage pFET and method of making same  
A zero threshold voltage (ZVt) pFET ( 104 ) and a method of making the same. The ZVt pFET is made by implanting a p-type substrate ( 112 ) with a retrograde n-well ( 116 ) so that a pocket ( 136 )...
6822297 Additional n-type LDD/pocket implant for improving short-channel NMOS ESD robustness  
A short-channel NMOS transistor in a p-well, bordered laterally on each side by an isolation region and vertically by a channel stop region, has a n-source and a n-drain, each comprising a shallow...
6821834 Ion implantation methods and transistor cell layout for fin type transistors  
Fin-type field effect transistors are fabricated on a semiconductor substrate. Rectangular fins are formed on the substrate in a rectangular pattern of rows and columns and gate electrodes are...
6815765 Semiconductor device with function of modulating gain coefficient and semiconductor integrated circuit including the same  
A semiconductor device has a structure in which an impurity diffusion region with an impurity concentration lower than an impurity concentration of a source and a drain is formed between the source...
6803630 Method of adjusting program voltage in non-volatile memories, and process for fabricating a non-volatile memory device  
The invention relates to a method of adjusting the erase/program voltage in semiconductor non-volatile memories. The memories are formed of at least one matrix of memory cells having a floating...
Matches 1 - 50 out of 326 1 2 3 4 5 6 7 >