Matches 401 - 450 out of 1638 < 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 >
Match Document Document Title
7179710 Method for fabricating NAND type dual bit nitride read only memory  
A NAND type dual bit nitride read only memory and a method for fabricating thereof are provided. Firstly, a plurality of isolation layers, which are spaced and parallel to each other are formed in...
7180128 Non-volatile memory, non-volatile memory array and manufacturing method thereof  
A non-volatile memory is provided. A plurality of stacked gate structure is formed on the substrate. The stacked gate structure includes, upward from the substrate surface, a select gate dielectric...
7176516 Structure and fabricating method to make a cell with multi-self-alignment in split gate flash  
A new structure is disclosed for semiconductor devices with which contact regions are self-aligned to conductive lines. Openings to a gate oxide layer, in partially fabricated devices on a silicon...
7176519 Memory cell, memory cell arrangement and method for the production of a memory cell  
A memory cell, memory cell arrangement, and method for producing a memory cell arrangement is described where electric charge carriers can be introduced from a trench structure, which delivers...
7176518 Nonvolatile flash memory device  
A method of fabricating nonvolatile memory devices is disclosed. A nonvolatile memory device comprises: a polysilicon gate on a semiconductor substrate; a gate oxide layer between the polysilicon...
7177505 MEMS-based actuator devices using electrets  
Electrets are used in a variety of MEMS-based actuator devices. The electret is able to store electrical charge for a long time with negligible charge leakage. Therefore, when an electret is...
7176077 Methods of forming memory cells and arrays having underlying source-line connections  
Floating-gate memory cells having a trench source-line contact are suited for increased packing densities without a need for low-resistance ground straps placed at regular intervals across a memory...
7173304 Method of manufacturing devices comprising conductive nano-dots, and devices comprising same  
A method is disclosed that may include forming a first layer of insulating material above a semiconducting substrate, forming an aluminum oxide layer above the first layer of insulating material,...
7173296 Reduced hydrogen sidewall spacer oxide  
An embodiment of the invention is a method of making a semiconductor structure 10 where the spacer oxide layer 90 is formed by a hydrogen free precursor CVD process. Another embodiment of the...
7172937 Method of manufacturing a non-volatile memory cell  
The present invention relates to a method of manufacturing a non-volatile memory cell. The method comprises forming an ONO stack and a mask formed on the ONO stack, providing a first etching...
7170129 Non-volatile memory, fabrication method thereof and operation method thereof  
A method of fabrication a non-volatile memory is provided. A stacked structure is formed on a substrate, the stacked structure including a gate dielectric layer and a control gate. Then, a first...
7166886 DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators  
Structures and methods for memory cells having a volatile and a non-volatile component in a single memory cell are provided. The memory cell includes a first source/drain region and a second...
7164294 Method for forming programmable logic arrays using vertical gate transistors  
One aspect disclosed herein relates to a method for forming a programmable logic array. Various embodiments of the method include forming a first logic plane and a second logic plane, each...
7160777 Split-gate nonvolatile memory device and method of manufacturing the same  
Embodiments of the invention include a gate insulating layer formed on a semiconductor substrate; a spacer-type floating gate and a spacer-type dummy pattern, which are formed on the gate...
7160774 Method of forming polysilicon layers in non-volatile memory  
In accordance with an embodiment of the present invention, a semiconductor structure includes an undoped polysilicon layer, a doped polysilicon layer in contact with the undoped polysilicon layer,...
7157768 Non-volatile flash semiconductor memory and fabrication method  
In a semiconductor memory, a plurality of FinFET arrangements with trapping layers or floating gate electrodes as storage mediums are present on respective top sides of fins made from semiconductor...
7157767 Semiconductor memory element, semiconductor memory arrangement, method for fabricating a semiconductor memory element and method for operating a semiconductor memory element  
A semiconductor memory element has a substrate, in which a source region and a drain region are formed, a floating gate electrically insulated from the substrate, and a tunnel barrier arrangement,...
7157332 Method for manufacturing flash memory cell  
Disclosed is a method for manufacturing a flash memory cell. A structure in which a floating gate, an ONO dielectric film and a control gate are stacked is formed by means of a gate mask process...
7154138 Transistor-arrangement, method for operating a transistor arrangement as a data storage element and method for producing a transistor-arrangement  
The invention relates to a transistor arrangement having a substrate and a vertical transistor comprising: a first electrode region, a second electrode region arranged essentially above the latter,...
7154153 Memory device  
A floating gate transistor has a reduced barrier energy at an interface with an adjacent gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is stored...
7151292 Dielectric memory cell structure with counter doped channel region  
A charge trapping dielectric memory cell array comprises a plurality of parallel bit lines implanted within the lightly doped substrate. The parallel bit lines define a plurality of channel regions...
7148106 Methods of fabricating non-volatile memory devices including nanocrystals  
Non-volatile memory devices can be fabricated by forming a tunnel dielectric layer on a semiconductor substrate, subjecting the semiconductor substrate having the tunnel dielectric layer to an...
7148578 Semiconductor multi-chip package  
A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is...
7149113 Semiconductor integrated circuit device  
To reduce cost of defect redundancy and trimming in a semiconductor integrated circuit having multiple layer wirings and copper wirings, an address for salvaging a defect of a memory cell array in...
7148537 Semiconductor memory device  
A semiconductor memory device includes a semiconductor substrate, a gate insulating film on the semiconductor substrate, a gate electrode on the gate insulating film, control insulating films...
7145208 MOS transistor having a work-function-dominating layer  
A MOS transistor including a substrate, a gate dielectric layer on the substrate, a stacked gate on the gate dielectric layer, and a source/drain in the substrate beside the stacked gate is...
7145200 Nonvolatile semiconductor memory device  
A nonvolatile semiconductor memory device includes a semiconductor substrate, a memory cell region which is disposed on the semiconductor substrate and has a transistor array of a stacked gate...
7144773 Method for preventing trenching in fabricating split gate flash devices  
A method for forming a split gate flash device is provided. In one embodiment, a semiconductor substrate with a dielectric layer formed thereover is provided. A conductor layer is formed overlying...
7141838 Buried word line memory integrated circuit system  
An integrated circuit system includes providing a semiconductor substrate and forming buried word lines in the semiconductor substrate with the buried word lines including vertical charge-trapping...
7141835 Semiconductor memory device having memory cells requiring no refresh operation  
A memory cell includes first and second data holding portions for holding stored data and its inverted data. First and second p channel TFT compensate for charges leaked from first and second...
7141474 Fabrication method of a nonvolatile semiconductor memory  
A method of fabricating a nonvolatile semiconductor memory including the steps of: sequentially forming a gate insulating layer and a first conductive layer of a floating gate on a semiconductor...
7141850 Gated semiconductor assemblies and methods of forming gated semiconductor assemblies  
In one aspect, the invention includes a method of forming a gated semiconductor assembly, comprising: a) forming a silicon nitride layer over and against a floating gate; and b) forming a control...
7141824 Transistor with variable electron affinity gate  
A SiC material composition is selected to establish the barrier energy between the SIC gate and a gate insulator. Various embodiments of selected SiC material composition include a memory...
7138680 Memory device with floating gate stack  
A memory device comprises a substrate including isolation regions and active regions, and a floating gate stack proximate the substrate. The floating gate stack comprises a first high-k dielectric...
7138679 Semiconductor memory device  
A semiconductor memory device comprises a silicon substrate having a main surface, a trench formed on the silicon substrate to open in the main surface and a memory cell formed on the trench. The...
7135736 Semiconductor device  
This specification relates to a semiconductor device that comprises a semiconductor substrate 11 , a source region 12 and a drain region 13 , which are formed on the semiconductor substrate 11...
7135734 Graded composition metal oxide tunnel barrier interpoly insulators  
Structures and methods for programmable array type logic and/or memory devices with graded composition metal oxide tunnel barrier intergate insulators are provided. The programmable array type...
7132711 Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers  
Structures and methods for programmable array type logic and/or memory with p-channel devices and asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type...
7132718 Fabrication method and structure of semiconductor non-volatile memory device  
A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a...
7132331 Non-volatile semiconductor memory devices having self-aligned gate conductive layers and methods of fabricating such devices  
A semiconductor device having a self-aligned gate conductive layer and a method of fabricating the same are disclosed. In embodiments of the present invention, a plurality of field isolation...
7129540 Semiconductor circuit arrangement with trench isolation and fabrication method  
An explanation is given of, inter alia, a circuit arrangement containing a trench which penetrates through a charge-storing layer ( 18 ) and a doped semiconductor layer ( 14 ). The trench...
7126183 Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers  
Structures and methods for programmable array type logic and/or memory with p-channel devices and asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type...
7126184 Nonvolatile semiconductor memory device and a method of the same  
A reduction in size nonvolatile semiconductors for use in a memory device and an increase in the capacity thereof are promoted. Each memory cell of a flash memory is provided with a field effect...
7125769 Method of fabricating flash memory device  
A method of fabricating a flash memory devices disclosed wherein, upon formation of sidewall oxide films, a regrown thickness of a screen oxide film is controlled. The width of an element isolation...
7122866 Semiconductor memory device with a stacked gate including a floating gate and a control gate and method of manufacturing the same  
A semiconductor memory device includes first and second MOS transistors. The first MOS transistor is formed on a region enclosed by a first element isolating region and includes a first gate...
7119384 Field effect transistor and method for fabricating it  
The invention relates to a field effect transistor in which the planar channel region on the upper surface of the elevation is extended in width by means of additional vertical channel regions on...
7118962 Nonvolatile memory device and method for manufacturing the same  
The present invention discloses a nonvolatile memory device which can improve the data storage capacity without increasing the surface area of the device, and a method for manufacturing the same. ...
7119393 Transistor having fully-depleted junctions to reduce capacitance and increase radiation immunity in an integrated circuit  
A floating-gate transistor for an integrated circuit is formed on a p-type substrate. An n-type region is disposed over the p-type substrate. A p-type region is disposed over the n-type region....
7115940 Semiconductor device  
A semiconductor device includes: a silicon substrate, having a main surface, in which trenches are formed; element isolation oxide films filling in trenches; a tunnel oxide film, formed on main...
7115470 Methods of fabricating flash memory cell having split-gate structure using spacer oxidation process  
There is provided a method of fabricating a split-gate flash memory cell using a spacer oxidation process. An oxidation barrier layer is formed on a floating gate layer, and an opening to expose a...
Matches 401 - 450 out of 1638 < 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 >