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7064376 High performance embedded semiconductor memory devices with multiple dimension first-level bit-lines  
A dynamic random access memory solves long-existing tight pitch layout problems using a multiple-dimensional bit line structure. Improvement in decoder design further reduces total area of this...
7061041 Memory device  
A memory device is provided. The memory device comprises a substrate, first isolation structures, stacked device structures, and second isolation structures. The substrate comprises a memory cell...
7061042 Double-cell memory device  
A memory array device has a plurality of gate structure lines, adjacently disposed over a substrate along a direction, wherein at least a portion of the gate structure lines have memory function. A...
7061808 Semiconductor memory device, driving method thereof, and portable electronic apparatus  
A semiconductor memory device includes a memory array; a storage section that receives a maximum pulse value from a user of the semiconductor memory device; a control section that executes a...
7061044 Non-volatile memory device  
A non-volatile memory device comprises a gate line that includes a gate dielectric layer, a bottom gate pattern, an inter-gate dielectric and a top gate pattern, which are sequentially stacked. The...
7057230 Nonvolatile semiconductor memory device employing transistors having different gate withstand voltages for enhanced reading speed  
A semiconductor device includes a plurality of nonvolatile memory cells ( 1 ). Each of the nonvolatile memory cells comprises a MOS type first transistor section ( 3 ) used for information storage,...
7057231 Nonvolatile memory cell with a floating gate at least partially located in a trench in a semiconductor substrate  
A floating gate ( 110 ) of a nonvolatile memory cell is formed in a trench ( 114 ) in a semiconductor substrate ( 220 ). A dielectric ( 128 ) covers the surface of the trench. The wordline ( 140 )...
7053449 Double gate transistor for low power circuits  
A double gate MOSFET having a control gate and a signal gate. The effective threshold voltage seen by the signal gate may be modified by charging the control gate. The effective threshold voltage...
7053441 Nonvolatile semiconductor memory device  
A nonvolatile semiconductor memory device having a small layout area includes a memory cell array in which a plurality of memory cells are arranged in a row direction and a column direction. The...
7053440 Non-volatile semiconductor memory device and manufacturing method of the same  
A non-volatile semiconductor memory device comprising: a first conductive type well formed within a semiconductor substrate; and a memory cell having a gate insulating film, a floating gate, an...
7053439 Chemoreceptive semiconductor structure  
A field effect transistor has a floating gate with an extended portion. A selectively chemoreceptive finger or layer is electrostatically coupled to the extended portion of the floating gate, and...
7053438 Fabrication of gate dielectric in nonvolatile memories in which a memory cell has multiple floating gates  
In fabrication of a nonvolatile memory cell having two floating gates, one or more peripheral transistor gates are formed from the same layer ( 140 ) as the select gate. The gate dielectric ( 130 )...
7053442 Nonvolatile semiconductor memory device  
A nonvolatile semiconductor memory device having a small layout area includes a memory cell array in which a plurality of memory cells are arranged in a row direction and a column direction. The...
7050331 Semiconductor memory device and portable electronic apparatus  
The present invention provides a semiconductor memory device including a memory cell array in which a plurality of memory cells are arranged, a user interface circuit including a command queue...
7049191 Method for protecting against oxidation of a conductive layer in said device  
In a semiconductor device including a first conductive layer, the first conductive layer is treated with a nitrogen/hydrogen plasma before an additional layer is deposited thereover. The treatment...
7049651 Charge-trapping memory device including high permittivity strips  
The charge-trapping layer comprises two strips above the source and drain junctions. The thicknesses of the charge-trapping layer and the gate dielectric are chosen to facilitate...
7049652 Pillar cell flash memory technology  
An array of a pillar-type nonvolatile memory cells ( 803 ) has each memory cell isolated from adjacent memory cells by a trench ( 810 ). Each memory cell is formed by a stacking process layers on a...
7049653 Nonvolatile semiconductor memory device having element isolating region of trench type  
A semiconductor device of a selective gate region having a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating...
7045851 Nonvolatile memory device using semiconductor nanocrystals and method of forming same  
A floating gate for a field effect transistor (and method for forming the same and method of forming a uniform nanoparticle array), includes a plurality of discrete nanoparticles in which at least...
7045845 Self-aligned vertical gate semiconductor device  
A transistor ( 10 ) is formed in a semiconductor substrate ( 12 ) whose top surface ( 48 ) is formed with a pedestal structure ( 24 ). A conductive material ( 40 ) is disposed along a side surface...
7045854 Non-volatile semiconductor memory  
An object of the present invention is to provide a semiconductor memory device suitable for larger-capacity storage because of its ability to store 3 or more bits in one element and capable of a...
7042039 Integrated memory circuit for storing a binary datum in a memory cell  
An integrated memory circuit includes at least one memory cell formed by a single transistor whose gate (GR) has a lower face insulated from a channel region by an insulation layer containing a...
7042043 Programmable array logic or memory devices with asymmetrical tunnel barriers  
Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or...
7038268 Nonvolatile semiconductor memory device  
In a nonvolatile semiconductor storage device which is electrically writable and erasable, a silicon substrate, a plurality of element isolation portions which project from the silicon substrate...
7038267 Non-volatile memory cell and manufacturing method thereof  
A non-volatile memory cell is provided. The non-volatile memory at least includes a substrate, a gate, a first source/drain region, a composite dielectric layer and a second source/drain region. A...
7038291 Semiconductor device and method of fabricating the same  
Provided is a semiconductor device and a method of fabricating the semiconductor device, in which electric characteristics of a gate insulating film thereof in the vicinity of an element isolation...
7034355 Nonvolatile semiconductor storage and its manufacturing method  
To achieve a higher operating speed, higher reliability, and lower power consumption by reducing the thickness of an inter-poly silicon insulator film between a floating gate and a control gate of...
7034354 Semiconductor structure with lining layer partially etched on sidewall of the gate  
A semiconductor structure with partially etched gate and method of fabricating the same. A semiconductor structure with a single-sided or dual-sided partially etched gate comprises a gate...
7029973 Method of fabricating a flash memory cell  
A method of forming a flash memory cell. A tunnel oxide layer, a floating gate layer, and a dielectric layer are formed on a substrate. A control gate layer is formed on the dielectric layer and...
7030448 Mask ROM and the method of forming the same and the scheme of reading the device  
The structure of the nonvolatile memory includes a substrate having source/drain formed at unselected sides and source/drain with extension source/drain formed at other selected sides. A gate...
7030444 Space process to prevent the reverse tunneling in split gate flash  
A split gate flash memory cell structure is disclosed for prevention of reverse tunneling. A gate insulator layer is formed over a semiconductor surface and a floating gate is disposed over the...
7030020 Method to shrink cell size in a split gate flash  
A new method to form MOS gates in an integrated circuit device is achieved. The method comprises forming a dielectric layer overlying a substrate. A polysilicon layer is formed overlying the...
7026682 Non-volatile memory device with enlarged trapping layer  
Methods for making a nonvolatile memory device, such as an NROM device that has an oxide-nitride-oxide layer beneath at least one word line structure, are disclosed. The oxide-nitride-oxide layer...
7026684 Nonvolatile semiconductor memory device  
Floating gates and control gates are alternately arranged on a substrate periodically in a first direction via a gate insulation film. Each floating gate has a first portion whose sectional shape...
7026683 Nonvolatile semiconductor memory device having grooves isolating the floating electrodes of memory cells and method of manufacturing the nonvolatile semiconductor memory device  
A plurality of nonvolatile memory elements formed on element regions respectively isolated by element isolation regions on a main surface of a first conductive type semiconductor substrate, the...
7026685 Semiconductor devices having a non-volatile memory transistor and methods for manufacturing the same  
Semiconductor devices including a non-volatile memory transistor and methods for manufacturing such semiconductor devices are described. One semiconductor device may include a silicon substrate ...
7026687 Non-volatile semiconductor memory and method of manufacturing the same  
A proposed non-volatile semiconductor memory and a method of manufacturing the same are directed to performing stable and highly reliable operations. First, grooves are formed in a p-type silicon...
7026212 Method for making high density nonvolatile memory  
An improved method for fabricating a three dimensional monolithic memory with increased density. The method includes forming conductors preferably comprising tungsten, then filling and planarizing;...
7023048 Nonvolatile semiconductor memory devices and the fabrication process of them  
The present invention enables to avoid a reduction in coupling ratio in a nonvolatile semiconductor memory device. The reduction is coupling ratio is caused due to difficulties in batch forming of...
7023046 Undoped oxide liner/BPSG for improved data retention  
Semiconductor devices with improved data retention are formed by depositing an undoped oxide liner on spaced apart transistors followed by in situ deposition of a BPSG layer. Embodiments include...
7023047 MOS device and process for manufacturing MOS devices using dual-polysilicon layer technology  
An MOS device has a stack and a passivation layer covering the stack. The stack is formed by a first polysilicon region and by a second polysilicon region arranged on top of one another and...
7023045 Layout of a flash memory having symmetric select transistors  
A layout of flash memory having symmetric select transistors includes a memory cell array and a polysilicon gate. The polysilicon gate forms a plurality of select transistors in coordination with a...
7019353 Three dimensional flash cell  
A floating gate memory cell includes isolation regions between adjacent cells, and a staggered pattern of columns of cells. Word lines are formed parallel to control gate structures.
7019392 Storage apparatus, card type storage apparatus, and electronic apparatus  
A storage apparatus 10 is disclosed, that comprises a wiring substrate 11 having a first surface and a second surface, a flat type external connection terminal 12 a disposed on the first...
7019354 Electrically erasable programmable read only memory (EEPROM) cells and methods of fabricating the same  
Electrically erasable programmable read only memory (EEPROM) cells and methods of fabricating the same are provided. An EEPROM cell includes an isolation layer formed at a semiconductor substrate...
7015534 Encapsulated MOS transistor gate structures and methods for making the same  
Transistor gate structures, encapsulation structures, and fabrication techniques are provided, in which sidewalls of patterned gate structures are conditioned by nitriding the sidewalls of the gate...
7015550 Nonvolatile semiconductor memory device  
A memory cell and a selection transistor for selecting the memory cell are provided. The memory cell includes a floating gate formed on a semiconductor substrate via a first gate insulation film, a...
7015537 Isolation-less, contact-less array of nonvolatile memory cells each having a floating gate for storage of charges, and methods of manufacturing, and operating therefor  
An isolation-less, contact-less nonvolatile memory array has a plurality of memory cells each with a floating gate for the storage of charges thereon, arranged in a plurality of rows and columns....
7015541 Memory cell including stacked gate sidewall patterns and method for fabricating same  
A memory cell and a method for fabricating same. The memory cell comprises a source region and a drain region formed in a semiconductor substrate and a channel region defined between the source and...
7015098 Methods and structure for an improved floating gate memory cell  
A method and structure for an improved floating gate memory cell are provided. The non volatile memory cell includes a substrate and a first insulating layer formed on the substrate. The memory...
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