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6878589 Method and system for improving short channel effect on a floating gate device  
A method and system for improving short channel effect on a floating gate device is disclosed. In one embodiment, a p-type implant is applied to a source side of the floating gate device. In...
6878988 Non-volatile memory with induced bit lines  
An electrically programmable non-volatile memory cell is provided. A semiconductor substrate is prepared. A pair of spaced apart source/drain (S/D) regions is defined on the semiconductor...
6878987 Split gate memory device  
A split gate memory device and fabricating method thereof, wherein gate insulating and polysilicon layers are sequentially formed on a substrate. The polysilicon layer is patterned and a capping...
6876033 Electrically erasable and programmable non-volatile memory cell  
An electrically erasable and programmable memory cell is provided. The memory cell includes a floating gate MOS transistor and a bipolar transistor for injecting an electric charge into the...
6876030 Semiconductor memory device  
A semiconductor memory device includes a field-effect transistor with a gate electrode that has been formed over a semiconductor substrate with a ferroelectric layer interposed between the...
6872614 Nonvolatile semiconductor memory device and process of production and write method thereof  
A nonvolatile semiconductor memory device featuring a reducing operating voltage while maintaining a good disturbance characteristic and high speed in a write operation, including a gate insulating...
6873005 Programmable memory devices supported by semiconductor substrates  
The invention includes a memory device supported by a semiconductor substrate and comprising in ascending order from the substrate: a floating gate, a dielectric material, a layer consisting...
6870180 Organic polarizable gate transistor apparatus and method  
An apparatus having a circuit coupled to the gate contact of field effect transistor wherein the transistor's gate includes a dielectric layer of which at least a portion is an organic dielectric....
6869837 Methods of fabricating a word-line spacer for wide over-etching window on outside diameter (OD) and strong fence  
A method of fabricating word-line spacers comprising the following steps. A substrate having an inchoate split-gate flash memory structure formed thereover is provided. A conductive layer is formed...
6870212 Trench flash memory device and method of fabricating thereof  
A method of fabricating a trench flash memory device, where the method includes forming a patterned mask layer on the substrate and using it as the mask for form a trench in the substrate. Next, a...
6867464 Supply voltage reduction circuit for integrated circuit  
An integrated circuit device is described which includes a voltage reduction circuit to reduce an externally supplied voltage using a transistor threshold drop. The transistor is fabricated in a...
6864523 Self-aligned source pocket for flash memory cells  
An improved method for forming a flash memory is disclosed. A self-aligned source implanted pocket located underneath and around the source line junction is formed after the field oxide between...
6861707 Negative differential resistance (NDR) memory cell with reduced soft error rate  
An active negative differential resistance element (an NDR FET) and a memory device (such as an SRAM) using such elements is disclosed Soft error rate (SER) performance for NDR FETs and such memory...
6861696 Structure and method for a two-bit memory cell  
According to one exemplary embodiment, a two-bit memory cell situated over a substrate comprises a tunnel oxide layer situated over the substrate. The two-bit memory cell further comprises a first...
6861689 One transistor DRAM cell structure and method for forming  
A single transistor DRAM cell is formed in a SOI substrate so that the DRAM cells are formed in bodies that are electrically isolated from each other. Each cell has doped regions that act as source...
6858497 Non-volatile semiconductor memory device and a method of producing the same  
The present invention prevents production of residue which causes short-circuit between word lines. A memory cell comprises a channel formation region CH, charge storage films CSF each comprised of...
6858862 Discrete polymer memory array and method of making same  
The invention relates to discrete, spaced-apart ferroelectric polymer memory device embodiments. The ferroelectric polymer memory device is fabricated by spin-on polymer processing and etching...
6855989 Damascene finfet gate with selective metal interdiffusion  
A fin field effect transistor includes a fin, a source region, a drain region, a first gate electrode and a second gate electrode. The fin includes a channel. The source region is formed adjacent a...
6855602 Method for forming a box shaped polygate  
A method for forming an improved etching hardmask oxide layer in a polysilicon etching process including providing a planarized semiconductor wafer process surface including adjacent first exposed...
6853027 Semiconductor nonvolatile memory with low programming voltage  
A semiconductor nonvolatile memory cell comprised of a p-type silicon well 12 , an n + drain 8 and an n + source 10 , the source and the drain regions defining an channel region 7 . On top...
6853028 Non-volatile memory device having dummy pattern  
A non-volatile memory device includes a cell region and a peripheral circuit region at the semiconductor substrate. A plurality active regions are disposed in the cell region in parallel with each...
6849890 Semiconductor device and manufacturing method thereof  
A semiconductor device comprises a semiconductor substrate having first conductivity type, a trench capacitor, provided in the substrate, having a charge accumulation region, a gate electrode...
6847088 Non-volatile semiconductor memory devices and methods for manufacturing the same  
Examples including non-volatile semiconductor memory devices in which digitized image data and voice data can be more efficiently written and read, and methods for manufacturing the same, are...
6844603 Nonvolatile NOR two-transistor semiconductor memory cell and associated NOR semiconductor memory device and method for the fabrication thereof  
The invention relates to a nonvolatile NOR two-transistor semiconductor memory cell, an associated semiconductor memory device and a method for the fabrication thereof, in which one-transistor...
6844584 Memory cell, memory cell configuration and fabrication method  
Each memory cell is a memory transistor which is provided on a top side of a semiconductor body and has a gate electrode which is arranged in a trench located between a source region and a drain...
6844590 Semiconductor device with trench isolation between two regions having different gate insulating films  
The major surface of a semiconductor substrate of a semiconductor device includes first and second regions and a boundary area therebetween. A first gate insulating film and a first gate electrode...
6842374 Method for operating N-channel electrically erasable programmable logic device  
An electrically erasable programmable logic device (EEPLD) contains a P-type substrate. A first N-type doped region is disposed in the P-type substrate. A first gate, which is used to store data,...
6841822 Static random access memory cells  
A static random access memory cell comprising a first invertor including a first p-channel pullup transistor, and a first n-channel pulldown transistor in series with the first p-channel pullup...
6833297 Method for reducing drain induced barrier lowering in a memory device  
The present invention is a method for fabricating a memory device. In one embodiment, a first impurity concentration is deposited in a channel region of a memory device. A second impurity...
6831325 Multi-level memory cell with lateral floating spacers  
A multi-level non-volatile memory transistor is formed in a semiconductor substrate. A conductive polysilicon control gate having opposed sidewalls is insulatively spaced just above the substrate....
6828624 Nonvolatile semiconductor memory device covered with insulating film which is hard for an oxidizing agent to pass therethrough  
A nonvolatile semiconductor memory device includes comprises: an element isolation region being in contact with a first element region, an insulating film covering a memory cell, a peripheral...
6828623 Floating gate memory device with homogeneous oxynitride tunneling dielectric  
A memory device with homogeneous oxynitride tunneling dielectric. Specifically, the present invention describes a flash memory cell that includes a tunnel oxide dielectric layer including...
6828183 Process for high voltage oxide and select gate poly for split-gate flash memory  
A process for forming a high voltage oxide (HV) and a select gate poly for a split-gate flash memory is disclosed. The general difficulty of forming oxides of two different thicknesses for two...
6828618 Split-gate thin-film storage NVM cell  
A semiconductor nonvolatile memory cell ( 30 ) comprising a split-gate FET device having a charge-storage transistor ( 38 ) in series with a select transistor ( 39 ). A multilayered charge-storage...
6828619 Nonvolatile semiconductor storage device  
A nonvolatile semiconductor storage device has a semiconductor substrate, a gate electrode formed on a surface of the semiconductor substrate, and a first diffusion layer and a second diffusion...
6825517 Ferroelectric transistor with enhanced data retention  
Data retention of a ferroelectric transistor is extended by intecting holes or electrons into the ferroelectric transistor when power is removed. The ferroelectric FET has a mechanism to trap...
6825523 Process for manufacturing a dual charge storage location memory cell  
A process for manufacturing a dual charge storage location electrically programmable memory cell that includes the steps of forming a central insulated gate over a semiconductor substrate; forming...
6825524 Semiconductor integrated circuit device  
A semiconductor integrated circuit device includes: a substrate; a first conductivity type of semiconductor layers arranged above the substrate as being insulated from the substrate and insulated...
6822285 EEPROM with multi-member floating gate  
An EEPROM device constructed in a first active area having a multi-element floating gate structure, including a central polysilicon body surrounded by a polysilicon spacer element and mutually...
6822926 Non-volatile semiconductor memory device  
A non-volatile semiconductor memory device having a memory cell array region in which a plurality of memory cells, each having first and second MONOS memory cells controlled by a word gate and...
6822284 ONO dielectric for memory cells  
A method of fabricating a semiconductor device includes providing a wafer substrate, forming a first oxide layer over the wafer substrate using a single wafer low pressure chemical vapor deposition...
6818512 Split-gate flash with source/drain multi-sharing  
A multi-bit split-gate (MSG) flash cell with multi-shared source/drain and making of the same are disclosed. The MSG is formed with N+1 stacked gates comprising floating gates and control gates,...
6818462 METHOD OF DETERMINING THE ACTIVE REGION WIDTH BETWEEN SHALLOW TRENCH ISOLATION STRUCTURES USING A C-V MEASUREMENT TECHNIQUE FOR FABRICATING A FLASH MEMORY SEMICONDUCTOR DEVICE AND A DEVICE THEREBY FORMED  
A method of determining the active region width ( 10 ) of an active region ( 4 ) by measuring the respective capacitance values (C 100 , C 100′ , C 100″ ) of respective composite capacitance...
6818942 Non-volatile semiconductor storage device having conductive layer surrounding floating gate  
In a non-volatile semiconductor storage device, a barrier layer is disposed, via an interlayer isolating film, in an area surrounding a floating gate, including an area adjoining a connecting part...
6815755 Non-volatile memory cells, high voltage transistors and logic transistors integrated on a single chip  
Semiconductor device having on a single substrate ( 1 ) at least one memory cell ( 3 ) and at least one logic transistor ( 25 ); the at least one memory cell having a floating gate ( 5 ), a tunnel...
6812515 Polysilicon layers structure and method of forming same  
A non-volatile memory cell includes a first insulating layer over a substrate region, and a floating gate. The floating gate includes a first polysilicon layer over the first insulating layer and a...
6812514 High density floating gate flash memory and fabrication processes therefor  
A floating gate flash memory device including a substrate including a source region, a drain region and a channel region positioned therebetween; a stack gate including a floating gate electrode,...
6812521 Method and apparatus for improved performance of flash memory cell devices  
Dopant of an n-type is deposited in the channel area of a p-type well of isolated gate floating gate NMOS transistors forming the memory cells of a memory device array connected in a NAND gate...
6809371 Semiconductor memory device and manufacturing method thereof  
A semiconductor memory device which more reliably retains electrons trapped in its charge-trapping regions. A high-dielectric gate insulating film is grown on a semiconductor substrate. This gate...
6808987 Vertical nitride read-only memory cell and method for forming the same  
A method for forming a vertical nitride read-only memory cell. A substrate having at least one trench is provided. A first conductive layer is formed in the lower trench and insulated from the...
Matches 501 - 550 out of 1034 < 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 >