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6953962 Nonvolatile memory device having a gate electrode  
A nonvolatile memory device having a gate electrode including: a non volatile memory cell configured to store data, and having a first gate electrode, first and second diffusion layers, the first...
6953963 Flash memory cell  
A flash memory cell including a p-type substrate, an n-type deep well, a stacked gate structure, a source region, a drain region, a p-type pocket doped region, spacers, a p-type doped region and a...
6952030 High-density three-dimensional memory cell  
A three dimensional monolithic memory comprising a memory cell allowing for increased density is disclosed. In the memory cell of the present invention, a bottom conductor preferably comprising...
6952027 Semiconductor integrated circuit device and electronic card using the same  
A semiconductor integrated circuit device includes a semiconductor region of a first conductivity type. A first insulated-gate field effect transistor having a source/drain region of a second...
6952034 Semiconductor memory array of floating gate memory cells with buried source line and floating gate  
A method of forming an array of floating gate memory cells, and an array formed thereby, wherein each memory cell includes a trench formed into a surface of a semiconductor substrate, and spaced...
6952017 Low-voltage and interface damage-free polymer memory device  
One embodiment of the invention relates to a polymer memory device and a method of making it. The polymer memory device may include a composite or single layer of a ferroelectric polymer memory...
6949788 Nonvolatile semiconductor memory device and method for operating the same  
A nonvolatile semiconductor memory device having MONOS type memory cells of increased efficiency by hot electron injection and improved scaling characteristics includes a channel forming region in...
6949792 Stacked gate region of a memory cell in a memory device  
Semiconductor devices are disclosed utilizing at least one polysilicon structure in a stacked gate region according to the present invention. The stacked gate region includes a substrate, at least...
6943401 Flash memory cell with drain and source formed by diffusion of a dopant from a silicide  
The present invention is a flash memory manufacturing process that facilitates efficient fabrication of a flash memory cell. In one embodiment, a silicide (e.g., CoSi) is utilized as a diffusion...
6943400 Semiconductor device and its manufacturing method  
A semiconductor device including an IGFET (insulated gate field effect transistor) ( 30 ) is disclosed. IGFET ( 30 ) may include a source/drain area ( 15 ) having an impurity concentration...
6940121 Semiconductor memory cell  
A semiconductor memory cell includes a semiconductor substrate that defines a trench having trench walls. The semiconductor memory cell also includes a floating gate electrode positioned within the...
6940119 Non-volatile programmable and electrically erasable memory with a single layer of gate material  
The semiconducting memory device comprises a non-volatile programmable and electrically erasable memory cell with a single layer of grid material and comprising a floating grid transistor and a...
6940122 Flash EEPROM unit cell and memory array architecture including the same  
A high-density flash EEPROM (Electrically Erasable Programmable Read Only Memory) unit cell and a memory array architecture including the same are disclosed. The flash EEPROM unit cell comprises a...
6940120 Non-volatile semiconductor memory device and method of fabricating thereof  
A phosphorus-doped amorphous silicon film and a silicon nitride film are serially grown over a semiconductor substrate. The obtained stack is patterned so as to obtain word lines. A CVD oxide film...
6936886 High density SRAM cell with latched vertical transistors  
High density static memory cells and arrays containing gated lateral bipolar transistors which can be latched in a bistable on state. Each transistor memory cell includes two gates which are pulse...
6936882 Selective silicidation of gates in semiconductor devices to achieve multiple threshold voltages  
A semiconductor device includes a substrate and an insulating layer formed on the substrate. A first device may be formed on the insulating layer. The first device may include a first fin formed on...
6933554 Recessed tunnel oxide profile for improved reliability in NAND devices  
An improved NAND-type memory cell structure having improved reliability and endurance. Since a high risk area for oxide breakdown and/or current leakage exists in the tunnel oxide layer,...
6933556 Semiconductor memory with gate at least partially located in recess defined in vertically oriented semiconductor layer  
A semiconductor memory comprises: a first conductivity type semiconductor substrate and one or more memory cells each constituted of an island-like semiconductor layer having a recess on a sidewall...
6933555 Flash EEPROM with function bit by bit erasing  
A multi-bit split-gate (MSG) flash cell with multi-shared source/drain, a method of making and a method of programming the same are disclosed. Furthermore, a method of bit-by-bit erasing, in...
6933194 Method of manufacturing semiconductor device using STI technique  
A method of manufacturing a semiconductor device including forming a laminate structure which includes a gate insulation film on a semiconductor substrate and a gate electrode material film on the...
6930349 Flash memory  
A manufacturing method of a flash memory comprising forming a patterned first dielectric layer, forming a patterned first conductive layer and a patterned hard mask layer on a substrate. Next,...
6930348 Dual bit split gate flash memory  
The dual bit split gate flash memory of the invention comprises a plurality of memory cells wherein each memory cell comprises a select gate overlying a substrate and isolated from the substrate by...
6927446 Nonvolatile semiconductor memory device and its manufacturing method  
A first diffused layer and a second diffused layer are formed on the major surface of a silicon substrate. A first insulating layer, a second insulating layer or a semiconductor layer, and a third...
6917068 Semiconductor device having conductive structures formed near a gate electrode  
A semiconductor device is provided by forming a gate electrode and a dielectric layer below and adjacent the side surfaces of the gate electrode. Relatively thin conductive structures are formed...
6916713 Code implantation process  
The present invention provides a code implantation process for the mask read only memory (MROM). A gate oxide layer and a wordline are formed sequentially over a substrate having a buried bitline,...
6917070 Single-poly EPROM and method for forming the same  
A single-poly EPROM and method for forming the same. The single-poly EPROM has an isolation region disposed in a substrate to define a striped active area. A deep n-well is located under the...
6914288 EEPROM and EEPROM manufacturing method  
A memory transistor of an EEPROM has a floating gate electrode of a shape such that it covers the entirety of a tunnel film and a channel region and does not cover a region between the channel...
6911691 Nonvolatile semiconductor memory device  
To propose a new channel structure suitable for high efficiency source side injection, and provide a non-volatile semiconductor memory device and a charge injection method using the same. The...
6911704 Memory cell array with staggered local inter-connect structure  
A memory cell array comprises a two dimensional array of memory cells fabricated on a semiconductor substrate. The memory cells are arranged in a plurality of rows and a plurality columns. Each...
6908818 Contactless channel write/erase flash memory cell and its fabrication method  
A contactless channel write/erase flash memory cell structure and its fabricating method for increasing the level of integration is disclosed. The present invention utilizes a buried diffusion...
6909159 Method and apparatus to make a semiconductor chip susceptible to radiation failure  
Methods and apparatus are provided for reducing the overall radiation hardness of a semiconductor chip. A radiation detector and a failure memory are provided. A disable signal or signals is...
6908803 Methods for forming wordlines, transistor gates, and conductive interconnects, and wordline, transistor gate, and conductive interconnect structures  
The invention encompasses stacked semiconductor devices including gate stacks, wordlines, PROMs, conductive interconnecting lines, and methods for forming such structures. The invention also...
6906376 EEPROM cell structure and array architecture  
An EEPROM cell device on a substrate is achieved. The device comprises, first, a selection transistor having gate, drain, source, and channel. The drain is defined as a cell bit line. An isolation...
6906377 Flash memory cell and fabrication thereof  
A flash memory cell is described, including at least a substrate, a tunnel oxide layer, a floating gate, an insulating layer, a control gate and an inter-gate dielectric layer. The tunnel oxide...
6903405 Semiconductor memory device with a pair of floating gates  
A floating gate is provided in the form of two separated parts in one memory cell to allow each of the floating gates to be individually programmable, thereby enabling the integration to be doubled...
6903407 Non volatile charge trapping dielectric memory cell structure with gate hole injection erase  
A dielectric memory cell comprises a substrate which includes a source region, a drain region, and a channel region positioned there between. A multilevel charge trapping dielectric is positioned...
6897506 Systems and methods using non-volatile memory cells  
Described in this disclosure is a non-volatile memory cell. The non-volatile memory cell generally includes a short-range atomic order substrate, a dielectric positioned adjacent to the substrate,...
6897514 Two mask floating gate EEPROM and method of making  
There is provided a floating gate transistor, such as an EEPROM transistor, and method of making the transistor using two masking steps. The method of making a transistor includes patterning a...
6894341 Semiconductor device and manufacturing method  
A semiconductor device comprises a memory cell array portion and peripheral circuit portion, wherein a first insulation film including elements as main components other than nitrogen fills between...
6894343 Floating gate memory cells utilizing substrate trenches to scale down their size  
Several embodiments of flash EEPROM split-channel cell arrays are described that position the channels of cell select transistors along sidewalls of trenches in the substrate, thereby reducing the...
6894340 Non-volatile semiconductor memory cell utilizing poly-edge discharge  
A process and structure for fabricating a non-volatile memory cell through the formation of a source and drain region and a charge trapping layer located therebetween is presented. E-fields for...
6894344 Semiconductor integrated circuit having two switch transistors formed between two diffusion-layer lines  
A multi-storage nonvolatile memory of high density, high speed and high reliability has a memory transistor and switch transistors disposed on both the sides of the memory transistor. The memory...
6891220 Method of programming electrons onto a floating gate of a non-volatile memory cell  
A memory cell has a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The source region is formed...
6890820 Method of fabricating FLASH memory devices  
A method of fabricating split gate type FLASH memory device comprises forming trench device isolation layers in a substrate to define a plurality of parallel first active regions. A gate insulation...
6890819 Methods for forming PN junction, one-time programmable read-only memory and fabricating processes thereof  
A method for forming a PN junction is described. A stacked structure consisting of an N-doped (or P-doped) layer, a dielectric layer and a nucleation layer is formed, and then an insulating layer...
6888190 EEPROM with source line voltage stabilization mechanism  
A low-voltage nonvolatile memory array includes an N type semiconductor substrate having a memory region. A deep P well is formed in the semiconductor substrate. A cell N well is located within the...
6885059 Nonvolatile memory and semiconductor device  
A nonvolatile memory transistor with multi values being capable of suppressing a short channel effect is provided. In an active region of a memory transistor, stripe-shaped impurity regions...
6885044 Arrays of nonvolatile memory cells wherein each cell has two conductive floating gates  
In a nonvolatile memory array in which each cell ( 110 ) has two floating gates ( 160 ), for any two consecutive memory cells, one source/drain region ( 174 ) of one of the cells and one...
6882008 Semiconductor integrated circuit device  
A semiconductor integrated circuit device comprises a semiconductor substrate; an insulating layer formed on the semiconductor substrate; a semiconductor layer insulated from the semiconductor...
6882011 ESD protection device having reduced trigger voltage  
An ESD protection device having reduced trigger voltage is disclosed. A first MOS transistor includes a first gate, a first heavily doped region at one side of the first gate, and a second heavily...
Matches 451 - 500 out of 1034 < 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 >