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Match Document Document Title
6229173 Hybrid 5F2 cell layout for buried surface strap aligned to vertical transistor  
A method and structure for an integrated circuit chip which includes forming a storage capacitor in a vertical opening in a horizontal substrate, forming a conductive strap laterally extending from...
6222215 DRAM circuitry  
Methods of forming capacitors and related integrated circuitry are described. In a preferred embodiment, the capacitors form part of a dynamic random access memory (DRAM) cell. According to one...
6222218 DRAM trench  
The present invention relates to a process of fabricating semiconductor memory structures, particularly deep trench semiconductor memory devices wherein a temperature sensitive high dielectric...
6218693 Dynamic random access memory (DRAM) cell having a buried horizontal trench capacitor by a novel fabrication method  
An improved dynamic random access memory (DRAM) cell using a novel buried horizontal trench capacitor was achieved. A capacitor trench is etched in a silicon substrate. A first high-k dielectric...
6215646 Dielectric capacitor and method of manufacturing same, and dielectric memory using same  
A trench is formed by forming a photoresist film on an interlevel insulator and performing isoprotonic etching using the photresist film as a mask. A lower electrode layer made of platinum (Pt), a...
6215142 Analog semiconductor device and method of fabricating the same  
An analog semiconductor device capable of preventing open of interconnection lines and notching due to step between transistor and capacitor regions is disclosed. An analog semiconductor device...
6211544 Memory cell layout for reduced interaction between storage nodes and transistors  
A memory cell, in accordance with the invention, includes a trench formed in a substrate, and an active area formed in the substrate below a gate and extending to the trench. The active area...
6211543 Lead silicate based capacitor structures  
A capacitor and method of making is described incorporating a semiconductor substrate, a bottom electrode formed on or in the substrate, a dielectric layer of barium or lead silicate, and a top...
6204527 Semiconductor memory device and method for producing same  
A semiconductor memory device comprises: a semiconductor substrate; a semiconductor region of a first conductive type formed in the semiconductor substrate; a diffusion region of a second...
6198151 Semiconductor device, semiconductor integrated circuit device, and method of manufacturing same  
It is an object to integrate storing functions at a high density and make it possible to perform a stable operation even at a low power supply voltage. A MOS transistor including a gate electrode...
6198123 Shielded integrated circuit capacitor connected to a lateral transistor  
An integrated circuit (IC) capacitor offers reduced sensitivity to parasitic capacitance, reduced-size, and increased noise immunity, such as for use in digital-to-analog converters (DACs),...
6194736 Quantum conductive recrystallization barrier layers  
Reduced scale structures of improved reliability and/or increased composition options are enabled by the creation and use of quantum conductive recrystallization barrier layers. The quantum...
6194755 Low-resistance salicide fill for trench capacitors  
Trench capacitors are fabricated utilizing a method which results in a refractory metal salicide as a component of the trench electrode in a lower region of the trench. The salicide-containing...
6191442 DRAM memory with TFT superposed on a trench capacitor  
In order to correspond to high integration with large capacity of a semiconductor device, provided are a structure of the semiconductor device and a method for manufacturing the same in which a...
6191443 Capacitors, methods of forming capacitors, and DRAM memory cells  
Capacitors and methods of forming capacitors are disclosed. In one implementation, a capacitor comprises a capacitor dielectric layer comprising Ta 2 O 5 formed over a first capacitor electrode....
6188096 DRAM cell capacitor having increased trench capacitance  
A trench capacitor having an increased surface area. In one embodiment, the trench capacitor is a dual trench capacitor having a first trench and a second trench wherein inner walls of the trenches...
6188097 Rough electrode (high surface area) from Ti and TiN  
A technique for forming high surface area electrode or storage nodes for a capacitor and devices formed thereby, including depositing a first layer of conductive material on a substrate, such that...
6188095 61/4 f2 DRAM cell structure with four nodes per bitline-stud and two topological wordline levels  
A cell-quadropole cell structure is disclosed which extends the principle of sharing the bitline-stud between two different cells (arranged in a one-dimensional line, e.g. w-direction) further to...
6184548 DRAM cell and array to store two-bit data having merged stack capacitor and trench capacitor  
A twin bit DRAM cell capable of storing two bits of digital data as stored charge within the DRAM cell is disclosed. The twin bit DRAM cell has two pass transistors, a trench capacitor, and a stack...
6180973 Semiconductor memory device and method for manufacturing the same  
A semiconductor memory device includes a semiconductor substrate, an element isolation film formed on the substrate, element formation regions each defined in an island form in the surface of the...
6180972 Buried, implanted plate for DRAM trench storage capacitors  
A buried plate particularly suitable for formation of a common plate of a plurality of trench capacitors, such as are employed in dynamic random access memories, is formed by implantation of...
6180975 Depletion strap semiconductor memory device  
A memory cell structure which uses field-effect controlled majority carrier depletion of a buried strap region for controlling the access to a trench-cell capacitor is described. The buried strap...
6177696 Integration scheme enhancing deep trench capacitance in semiconductor integrated circuit devices  
A trench capacitor structure suitable for use in a semiconductor integrated circuit device and the process sequence used to form the structure. The trench capacitor provides increased capacitance...
6177697 Arrangement for DRAM cell using shallow trench isolation  
A semiconductor structure uses a shallow trench isolation (STI) region to realize a capacitor trench of a reduced size. Consistent with one embodiment of fabricating a memory cell, the invention...
6163045 Reduced parasitic leakage in semiconductor devices  
A trench capacitor having a diffusion region adjacent to the collar to increase the gate threshold voltage of the parasitic MOSFET. This enables the use of a thinner collar while still achieving a...
6157055 Semiconductor memory device having a long data retention time with the increase in leakage current suppressed  
In a semiconductor memory device such as a DRAM, a conductive film (1.11') is arranged on the rim portion of a isolation insulating film (1.2) in opposition to a semiconductor substrate (1.1) with...
6153901 Integrated circuit capacitor including anchored plug  
An integrated circuit capacitor includes a substrate with an interconnection line adjacent the substrate, and a first dielectric layer on the interconnection line. The first dielectric layer...
6153902 Vertical DRAM cell with wordline self-aligned to storage trench  
A dynamic random access memory (DRAM) device. The DRAM device is formed in a substrate having a top surface and a trench with a sidewall formed in the substrate. A signal storage node is formed...
6150686 Semiconductor integrated circuit device with trench capacitor and method of manufacturing the same  
A semiconductor integrated circuit device includes a p-silicon substrate, an n-buried layer formed in the substrate to divide the substrate into an upper region and a lower region, a trench formed...
6147378 Fully recessed semiconductor device and method for low power applications with single wrap around buried drain region  
A fully recessed device structure and method for low power applications comprises a trenched floating gate, a trenched control gate and a single wrap around buried drain region. The trenched...
6144055 Semiconductor memory device  
A dynamic memory device includes a buried plate-wiring connected to a plate electrode of a memory cell. A plate potential is supplied to the buried plate-wiring via a plate potential supply-wiring....
6144054 DRAM cell having an annular signal transfer region  
A memory device formed in a substrate having a trench with side walls formed in the substrate. The device includes a bit line conductor and a word line conductor. A signal storage node has a first...
6140675 Semiconductor device and manufacturing method thereof  
A semiconductor device provided with a thin film of 0.1 nm to 2 nm in thickness, having a crystal structure different from that of a conductor and a semiconductor region, between the conductor and...
6140673 Semiconductor memory device and fabricating method  
In a high-integration DRAM device using a SOI substrate, a conductive film for connecting the source region or the drain region to the polysilicon film filled in the trench is formed in an...
6140674 Buried trench capacitor  
An integrated circuit and a method of making the same are provided. The circuit includes a substrate that has a trench formed therein defining and isolating first and second active area and an...
6140175 Self-aligned deep trench DRAM array device  
An integrated circuit and a method of manufacturing an integrated circuit comprises forming an insulator over a substrate, forming a trench in the insulator and the substrate, undercutting the...
6137128 Self-isolated and self-aligned 4F-square vertical fet-trench dram cells  
A densely packed array of vertical semiconductor devices, having pillars, deep trench capacitors, vertical transistors, and methods of making thereof are disclosed. The pillars act as transistor...
6107153 Method of forming a trench capacitor for a DRAM cell  
A method for forming a trench capacitor of a dynamic random access memory cell is disclosed. The method includes patterning to etch a semiconductor substrate (10) of a first conductivity to form a...
6104054 Space-efficient layout method to reduce the effect of substrate capacitance in dielectrically isolated process technologies  
A method for reducing the parasitic capacitance and capacitive coupling of nodes (106) in a dielectrically isolated integrated circuit (100) using layout changes. A separate area of floating...
6097049 DRAM cell arrangement  
A DRAM cell arrangement and method for manufacturing same, wherein a storage capacitor is connected via a first source/drain zone of a vertical selection transistor and a bit line. Since the...
6090660 Method of fabricating a gate connector  
The present invention is a DRAM cell, comprising a transistor having a gate, the gate having an individual segment of gate conductor and a conductive spacer rail wordline in contact with the...
6081008 Composite trench-fin capacitors for DRAM  
A semiconductor memory device capacitor is disclosed which has a trench capacitor portion provided in a semiconductor substrate and a fin capacitor portion provided above the substrate. The trench...
6072208 Dynamic random access memory fabricated with SOI substrate  
In a dynamic random access memory (DRAM), a step produced by forming a stacked capacitor can be prevented from being produced and increased, thereby facilitating the patterning of an upper layer...
6054396 Semiconductor processing method of reducing thickness depletion of a silicide layer at a junction of different underlying layers  
A semiconductor processing method of reducing thickness depletion of a nitride layer at a junction of different underlying layers includes, a) providing a substrate, the substrate comprising a...
6043528 Semiconductor memory device having trench-type capacitor structure using high dielectric film and its manufacturing method  
A semiconductor memory device comprises a MOS-type transistor formed on a semiconductor substrate, a capacitor formed in the interior of an opening portion formed in the semiconductor substrate to...
6040595 Structure of a non-destructive readout dynamic random access memory  
A structure of dynamic random access memory includes a field effect transistor (FET), a capacitor, a world line and a bit line. The gate of the FET is electrically coupled to the word line in which...
6037620 DRAM cell with transfer device extending along perimeter of trench storage capacitor  
A structure and method of manufacture is disclosed herein for a semiconductor memory cell having size of 4.5 F2 or less, where F is the minimum lithographic dimension. The semiconductor memory cell...
6037210 Memory cell with transfer device node in selective polysilicon  
A memory cell is constructed with one electrode of the transfer device extending over a trench capacitor, saving about 6.5% of cell area. Selective polysilicon for a strap seeded from the trench is...
6034390 Multi-bit trench capacitor  
A multi-bit trench capacitor having first and second storage nodes provided in the lower region thereof is described. The storage nodes are separated by a dielectric layer that separates the...
6028346 Isolated trench semiconductor device  
MOS transistors connected to each other are electrically isolated at both ends of a transfer gate by an LOCOS oxide film, and the bottom surface in a trenched capacitor portion and the side wall of...
Matches 601 - 650 out of 866 < 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 >