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7015523 Ferroelectric memory structure and fabrication method thereof  
A ferroelectric memory structure is disclosed. The ferroelectric memory structure includes a substrate, an insulating layer formed on the substrate, a plurality of oxide electrodes formed on the...
7015525 Folded bit line DRAM with vertical ultra thin body transistors  
A folded bit line DRAM device is provided. The folded bit line DRAM device includes an array of memory cells. Each memory cell in the array of memory cells includes a pillar extending outwardly...
7012313 MOS transistor in a single-transistor memory cell having a locally thickened gate oxide  
A MOS transistor in a single-transistor memory cell having a locally thickened gate oxide, and a process for producing the transistor. The MOS transistor can be used as a selection transistor in a...
7012296 Semiconductor integrated circuit  
A multi-storage nonvolatile memory of high density, high speed and high reliability has a memory transistor and switch transistors disposed on both the sides of the memory transistor. The memory...
7009228 Guard ring structure and method for fabricating same  
A method for fabricating a guard ring structure for JFETs and MESFETs. Trenches are etched in a semiconductor substrate for fabrication of a gate structure for a JFET or MESFET. At time the gate...
7009262 Semiconductor device and manufacturing method thereof  
A manufacturing method of a semiconductor device which can decrease the degradation of an element due to plasma in the LDD formation process is provided. The degradation of an element due to plasma...
7005716 Dual metal gate process: metals and their silicides  
Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a...
6998681 Lateral low-side and high-side high-voltage devices  
Lateral high-side and low-side high-voltage devices with low specific on-resistances are made in a first and in a second surface voltage-sustaining region, respectively. In the on-state of...
6998658 Twin NAND device structure, array operations and fabrication method  
A method for making a twin MONOS memory array is described where two nitride storage sites lay under the memory cell word gate. The fabrication techniques incorporate self alignment techniques to...
6995428 High voltage LDMOS transistor having an isolated structure  
A high voltage LDMOS transistor according to the present invention includes a P-field and divided P-fields in an extended drain region of a N-well. The P-field and divided P-fields form...
6989559 Discrete circuit component having fabrication stage clogged through-holes and process of making the same  
A discrete circuit component is made from a substrate with the first and second surfaces thereof each having a corresponding matrix of electrically conductive segments. A plated through-hole...
6984568 Semiconductor memory device having multi-layered storage node contact plug and method for fabricating the same  
A semiconductor memory device includes a bit line stack and a storage node contact hole which are aligned at bit line spacers formed at both side walls of the bit line stack and exposes a pad. The...
6974752 Methods of fabricating integrated circuit devices having uniform silicide junctions  
A gate having sidewalls is formed on an integrated circuit substrate. A barrier layer spacer is formed on the sidewalls of the gate. A portion of the barrier layer spacer protrudes from the...
6974982 Method of manufacturing semiconductor device and semiconductor device  
Impurity ions are implanted into the silicon layer of an SOI substrate to achieve an ion concentration distribution which inhibits for a reduction in threshold voltage (Vth-rolloff) as a gate...
6967363 Lateral diode with multiple spacers  
Various circuit devices, including diodes, and methods manufacturing therefor are provided. In one aspect, a method manufacturing is provided that includes forming a gate structure on a...
6967364 Elevated photo diode in an image sensor  
The invention provides an elevated photodiode for image sensors and methods of formation of the photodiode. Elevated photodiodes permit a decrease in size requirements for pixel sensor cells while...
6963094 Metal oxide semiconductor transistors having a drain punch through blocking region and methods for fabricating metal oxide semiconductor transistors having a drain punch through blocking region  
Metal oxide semiconductor transistors and devices with such transistors and methods of fabricating such transistors and devices are provided. Such transistors may have a silicon well region having...
6960784 Charging sensor method and apparatus  
A charging sensor is provided to detect charging signal during the manufacturing process of integrated circuits and various semiconductor devices. In one embodiment, the charging sensor includes a...
6958500 Semiconductor device having low resistivity source and drain electrodes  
A dummy gate crossing an active area having ends in contact with an isolation area is formed. A low area lower than a dummy gate is formed in the isolation area. Side walls are formed in the active...
6956267 Semiconductor with a nitrided silicon gate oxide and method  
A method of fabricating a transistor includes providing a semiconductor substrate having a surface and forming a nitride layer outwardly of the surface of the substrate. The nitride layer is...
6952027 Semiconductor integrated circuit device and electronic card using the same  
A semiconductor integrated circuit device includes a semiconductor region of a first conductivity type. A first insulated-gate field effect transistor having a source/drain region of a second...
6949815 Semiconductor device with decoupling capacitors mounted on conductors  
A semiconductor device has an LSI device provided with a plurality of power supply line connection pads and ground line connection pad in a peripheral edge part of a circuit-formation surface,...
6940110 SiC-MISFET and method for fabricating the same  
A storage-type SiC-MISFET includes a SiC substrate, an n-type drift layer, a p-type well region, an n-type source region, a SiC channel layer which contains an n-type impurity and is to be a...
6940143 Semiconductor thin-film manufacturing method, semiconductor device manufacturing method, semiconductor device, integrated circuit, electro-optical device, and electronic appliance  
According to the semiconductor thin-film and semiconductor device manufacturing method of the present invention, an insulating film having a through-hole between two layers of silicon film is...
6936875 Insulated-gate field-effect transistor, method of fabricating same, and semiconductor device employing same  
With the invention, it is possible to avoid deterioration in short-channel characteristics, caused by a silicon germanium layer coming into contact with the channel of a strained SOI transistor....
6933555 Flash EEPROM with function bit by bit erasing  
A multi-bit split-gate (MSG) flash cell with multi-shared source/drain, a method of making and a method of programming the same are disclosed. Furthermore, a method of bit-by-bit erasing, in...
6930335 Field effect transistor with metal oxide gate insulator and sidewall insulating film  
Provided is a semiconductor device including a silicon substrate, a gate insulator disposed on the silicon substrate and containing a metal oxide, a gate electrode disposed on the gate insulator,...
6930346 Evaporation of Y-Si-O films for medium-K dielectrics  
A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO 2 gate oxides are provided. Gate oxides formed from...
6924536 Semiconductor device and its manufacturing method  
A semiconductor device and a method of manufacturing the semiconductor device are disclosed. A semiconductor device of one of several disclosed embodiments comprises a semiconductor layer having a...
6921933 Semiconductor device and method of fabricating the same  
A gate electrode is formed on a semiconductor substrate with agate insulating film interposed therebetween. A channel region composed of a first-conductivity-type semiconductor layer is formed in a...
6918284 Interconnected networks of single-walled carbon nanotubes  
An electronic device having an interconnected network of carbon nanotubes on the surface of a substrate, and two or more electrical leads. The network forms an electrical connection between the leads.
6919644 Semiconductor device manufacturing method and semiconductor device manufactured thereby  
A method of manufacturing a semiconductor device involves mounting a semiconductor chip, formed on top with a main electrode and a subelectrode smaller in area than the main electrode, on a die pad...
6911666 Flexible metal foil substrate display and method for forming same  
A flexible metal foil substrate organic light emitting diode (OLED) display and a method for forming the same are provided. The method comprises: supplying a metal foil substrate such as titanium...
6903393 Semiconductor device fabricated on surface of silicon having <110> direction of crystal plane and its production method  
In a semiconductor device in which a plurality of field effect transistors are formed on a silicon surface having substantially a <110> orientation, the field effect transistors are disposed...
6897102 Process to minimize polysilicon gate depletion and dopant penetration and to increase conductivity  
A method of preparing a polysilicon gate to minimize gate depletion and dopant penetration and to increase conductivity is revealed. Several monolayers of atomic are condensed onto a gate...
6897499 Semiconductor integrated circuit device including MISFETs each with a gate electrode extended over a boundary region between an active region and an element isolation trench  
A gate electrode of each MISFET is formed on a substrate in an active region whose periphery is defined by an element isolation trench, and crosses the active region so as to extend from one end...
6893949 Semiconductor devices having contact plugs and local interconnects and methods for making the same  
Provided is, for example, a method for the fabrication of electrical interconnects in semiconductor devices wherein a substrate including two or more transistors having gate regions wherein the...
6894334 Semiconductor integrated circuit device, process for fabricating the same, and apparatus for fabricating the same  
Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by...
6894330 Memory configuration and method for reading a state from and storing a state in a ferroelectric transistor  
The state of a ferroelectric transistor in a memory cell is read or stored, and the threshold voltage of further ferroelectric transistors in further memory cells in the memory matrix is increased...
6891213 Base current reversal SRAM memory cell and method  
A SRAM memory cell including an access device formed on a storage device is described. The storage device has at least two stable states that may be used to store information. In operation, the...
6891210 Semiconductor device having a protection circuit  
The semiconductor device includes a plurality of transistors, wherein one of the transistors that has the thinnest gate dielectric layer is selected to serve as a power source protection element,...
6888197 Power metal oxide semiconductor field effect transistor layout  
A power MOSFET layout according to one embodiment of the invention comprises a substrate and a plurality of cells. Each of the cells includes a base portion, a plurality of protruding portions...
6888183 Manufacture method for semiconductor device with small variation in MOS threshold voltage  
After a MOS type transistor is formed on the surface of a semiconductor substrate, an interlayer insulating film covering the transistor is formed. The insulating film includes a silicon oxide film...
6888195 Semiconductor device with alternating conductivity type layers having different vertical impurity concentration profiles  
A power semiconductor device is disclosed, which comprises a semiconductor layer including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second...
6885068 Storage element and SRAM cell structures using vertical FETs controlled by adjacent junction bias through shallow trench isolation  
A new digital follower device is achieved. The digital follower device comprises an n-channel vertical FET device and a p-channel vertical FET device. Each vertical FET device comprises a bulk...
6881987 pMOS device having ultra shallow super-steep-retrograde epi-channel with dual channel doping and method for fabricating the same  
The present invention provides a p-channel metal-oxide-semiconductor (pMOS) device having an ultra shallow epi-channel satisfying a high doping concentration required for a device of which gate...
6881991 Dry-etching method and apparatus, photomasks and method for the preparation thereof, and semiconductor circuits and method for the fabrication thereof  
A dry-etching method comprises the step of dry-etching a metal thin film as a chromium-containing film, wherein the method is characterized by using, as an etching gas, a mixed gas including (a) a...
6878988 Non-volatile memory with induced bit lines  
An electrically programmable non-volatile memory cell is provided. A semiconductor substrate is prepared. A pair of spaced apart source/drain (S/D) regions is defined on the semiconductor...
6878578 Method for forming a high quality chemical oxide on a freshly cleaned silicon surface as a native oxide replacement  
A continuous and integrated cleaning/preparation process is described to condition a silicon surface for the formation of a high quality ultra thin gate oxide described. The process is conducted...
6872994 Semiconductor device having an active region whose width varies  
A semiconductor device of the present invention has an active region whose width varies. Gate electrodes cross over narrowest portions of the active region. Therefore, the device is not prone to...
Matches 401 - 450 out of 845 < 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 >