Patents in Class 257/288

Matches 51 - 100 out of 838

Match	Document	Document Title
51	7566655	Integration process for fabricating stressed transistor structure A process flow integration scheme employs one or more techniques to control stress in a semiconductor device formed thereby. In accordance with one embodiment, cumulative stress contributed by RTP...
52	7564081	finFET structure with multiply stressed gate electrode A semiconductor structure and its method of fabrication include a semiconductor fin located over a substrate. A gate electrode is located over the semiconductor fin. The gate electrode has a first...
53	7564080	Method for producing a laser diode component, housing for a laser diode component, and laser diode component itself A method for producing a laser diode component having an electrically insulating housing basic body and electrical connecting conductors, which are led out from the housing basic body and are...
54	7564120	Electrical passivation of silicon-containing surfaces using organic layers Electrical structures and devices may be formed and include an organic passivating layer that is chemically bonded to a silicon-containing semiconductor material to improve the electrical...
55	7564061	Field effect transistor and production method thereof A field effect transistor having a gate, a source, and a drain formed from metallic materials is disclosed that is able to supply a high driving current. In the field effect transistor, a source...
56	7560762	Asymmetric floating gate NAND flash memory A NAND-type flash memory device includes asymmetric floating gates overlying respective wordlines. A given floating gate is sufficiently coupled to its respective wordline such that a large gate...
57	7560757	Semiconductor device with a structure suitable for miniaturization A semiconductor device which is suitable for miniaturization, capable of improving variations in characteristics of a transistor and enhancing the current driving capability comprises a...
58	7560759	Semiconductor device and method of manufacturing the same A fin type MOSFET and a method of manufacturing the fin type MOSFET are disclosed. Gate structures in the fin type MOSFET are formed by a damascene process without a photolithography process....
59	7560774	IC chip An IC chip, including a switch LDMOS device and an analog LDMOS device, is configured on a substrate having a first conductive type. Components of the two LDMOS devices respectively include two...
60	7560758	MOSFETs comprising source/drain recesses with slanted sidewall surfaces, and methods for fabricating the same The present invention relates to improved metal-oxide-semiconductor field effect transistor (MOSFET) devices with stress-inducing structures located at the source and drain (S/D) regions....
61	7557436	Semiconductor device and IC card including supply voltage wiring lines formed in different areas and having different shapes Wiring lines for the supply of a voltage to feed a drive voltage to an integrated circuit formed in a semiconductor chip are disposed so as to cover a main surface of the semiconductor chip, so...
62	7557395	Trench MOSFET technology for DC-DC converter applications A trench power semiconductor device including a recessed termination structure.
63	7557396	Semiconductor device and method of manufacturing semiconductor device A semiconductor device includes a side wall spacer formed on the side surface of a gate electrode formed on the upper side of a semiconductor substrate with a gate insulation film therebetween,...
64	7554152	Versatile system for integrated sense transistor The present invention provides a versatile system for producing sense transistors having optimized thermal and parametric matching with an associated power transistor. A power transistor is formed,...
65	7554139	Semiconductor manufacturing method and semiconductor device A production method for a semiconductor device according to the present invention includes: step (A) of providing a substrate including a semiconductor layer having a principal face, the substrate...
66	7554140	Nand-type non-volatile memory device Provided is a NAND-type nonvolatile memory device and method of forming the same. In the method, a plurality of cell layers are stacked on a semiconductor substrate. Seed contact holes for forming...
67	7550795	SOI devices and methods for fabricating the same Silicon on insulator (SOI) devices and methods for fabricating the same are provided. An exemplary embodiment of a SOI device comprises a substrate. A first insulating layer is formed over the...
68	7550796	Germanium semiconductor device and method of manufacturing the same A germanium semiconductor device and a method of manufacturing the same are provided. The method includes the steps of: forming an isolation layer on a substrate using a shallow trench; forming a...
69	7547930	High performance FET devices and methods thereof Structure and methods of fabrication are disclosed for an enhanced FET devices in which dopant impurities are prevented from diffusing through the gate insulator. The structure comprises a Si:C, or...
70	7545236	Electromechanical filter utilizing a quantum device and sensing electrode An electromechanical filter capable of attaining a size reduction and a higher integration and executing a high-sensitivity signal sensing is provided. A quantum device is used as a sensing portion...
71	7544981	Active matrix type semicondcutor display device There is provided an active matrix type semiconductor display device which realizes low power consumption and high reliability. In the active matrix type semiconductor display device of the present...
72	7544980	Split gate memory cell in a FinFET A memory cell is implemented using a semiconductor fin in which the channel region is along a sidewall of the fin between source and drains regions. One portion of the channel region has a select...
73	7544552	Method for manufacturing junction semiconductor device A method for manufacturing a junction semiconductor device, having a step for forming a first high-resistance layer, a step for forming a channel-doped layer, a step for forming a second...
74	7541645	Metal oxide semiconductor (MOS) transistors having buffer regions below source and drain regions A unit cell of a metal oxide semiconductor (MOS) transistor is provided including an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor has a...
75	7541656	Semiconductor devices with enlarged recessed gate electrodes A semiconductor device includes a semiconductor substrate having a recess therein. A gate insulator is disposed on the substrate in the recess. The device further includes a gate electrode...
76	7541629	Embedded insulating band for controlling short-channel effect and leakage reduction for DSB process A method and structure for reducing leakage currents in integrated circuits based on a direct silicon bonding (DSB) fabrication process. After recessing a top semiconductor layer and an underlying...
77	7538352	Semiconductor device and power converter, driving inverter, general-purpose inverter and high-power high-frequency communication device using same In a semiconductor device that uses a silicon carbide semiconductor substrate having p type, n type impurity semiconductor regions formed by ion implantation, the electrical characteristics of the...
78	7535051	Memory device and method of manufacturing the same A example embodiment may provide a memory device that may include an active pattern on a semiconductor substrate, a first charge trapping layer pattern on the active pattern, a first gate electrode...
79	7531849	High performance FET devices An epitaxially layered structure with gate voltage bias supply circuit element for improvement in performance for semiconductor field effect transistor (FET) devices utilizes a structure comprised...
80	7525162	Orientation-optimized PFETS in CMOS devices employing dual stress liners A PFET is provided on a silicon layer having a (110) surface orientation and located in a substrate. A compressive stress liner disposed on the gate and source/drain regions of the PFET generates a...
81	7525118	Test element group, method of manufacturing a test element group, method of testing a semiconductor device, and semiconductor device To provide a TEG capable of early stage feedback of testing contents and a method of testing using the TEG. TFTs for TEG are manufactured on a different substrate than actual panel TFTs by using...
82	7521747	Vertical transistor and a semiconductor integrated circuit apparatus having the same AMOS transistor comprises: a first conduction type region; a second conduction type drain region formed on the outermost layer portion of the first conduction type region; a second conduction type...
83	7521741	Shielding structures for preventing leakages in high voltage MOS devices A high-voltage MOS device includes a first high-voltage well (HVW) region overlying a substrate, a second HVW region overlying the substrate, a third HVW region of an opposite conductivity type as...
84	7521740	Semiconductor device comprising extensions produced from material with a low melting point A semiconductor device comprises a gate electrode ( 1 ) and a gate insulating layer ( 2 ) both surrounded by a spacer ( 3 ) and produced on a surface (S) of a substrate ( 100 ) of a first...
85	7518171	Photo diode and related method for fabrication A method for fabricating a photo diode first involves providing a substrate. A doping area is then formed on the substrate. Afterwards, a dielectric layer, and a first poly-silicon layer are formed...
86	7518246	Atomic layer deposition of CeO₂/Al₂O₃films as gate dielectrics The use of atomic layer deposition (ALD) to form a nanolaminate layered dielectric layer of cerium oxide and aluminum oxide acting as a single dielectric layer with a ratio of approximately two to...
87	7518169	MOS-transistor on SOI substrate with source via In an inventive MOS transistor having a source region, a drain region and a channel region, which are formed in a semiconductor layer of an SOI substrate, which has a semiconductor substrate below...
88	7514756	Semiconductor device with MISFET A semiconductor device includes a substrate, a semiconductor region provided in the substrate, a group of transistors including a plurality of MIS transistors and provided in the semiconductor...
89	7514755	Integrated circuit modification using well implants A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed having a well of a first conductivity type under the gate region being...
90	7514762	Active matrix pixel device with photo sensor An active matrix pixel device including a plurality of polycrystalline silicon islands supported by a substrate, one of the polycrystalline silicon islands providing a channel and doped...
91	7514731	Switch elements and a DC/DC converter using the same A semiconductor device in which the self-turn-on phenomenon is prevented that can significantly improve power conversion efficiency. The semiconductor device is a system-in-package for power supply...
92	7514730	Method of fabricating a non-floating body device with enhanced performance Provided is a semiconductor transistor device including a substrate having at least two regions, a semiconductive region extending to a first surface of the substrate and an insulative region...
93	7511321	Method for forming a dielectric layer and related devices A dielectric layer may be formed by depositing the dielectric layer to an intermediate thickness and applying a nitridation process to the dielectric layer of intermediate thickness. The dielectric...
94	7510926	Technique for providing stress sources in MOS transistors in close proximity to a channel region A strained semiconductor material may be positioned in close proximity to the channel region of a transistor, such as an SOI transistor, while reducing or avoiding undue relaxation effects of metal...
95	7508031	Enhanced segmented channel MOS transistor with narrowed base regions By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor...
96	7504679	Enhancement mode GaN FET with piezoelectric gate One or more enhancement mode GaN devices has a stress-reduced gate region which interrupts the normally conductive 2Deg layer. A piezoelectric film is disposed over the stress-reduced gate region...
97	7504692	High-voltage field-effect transistor High-voltage field-effect transistor is provided that includes a drain terminal, a source terminal, a body terminal, and a gate terminal. A gate oxide and a gate electrode, adjacent to the gate...
98	7504693	Dislocation free stressed channels in bulk silicon and SOI CMOS devices by gate stress engineering Structures and methods of manufacturing are disclosed of dislocation free stressed channels in bulk silicon and SOI (silicon on insulator) CMOS (complementary metal oxide semiconductor) devices by...
99	7501674	Semiconductor device having fin transistor and planar transistor and associated methods of manufacture Disclosed is a fin transistor and a planar transistor and a method of forming the same. The fin transistor and the planar transistor are formed to have gate electrodes with similar thicknesses by...
100	7501673	Semiconductor device multilayer structure, fabrication method for the same, semiconductor device having the same, and semiconductor device fabrication method In one embodiment, a semiconductor device includes a semiconductor substrate and a doped conductive layer formed over the semiconductor substrate. A diffusion barrier layer is formed over the doped...

Matches 51 - 100 out of 838

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