Matches 551 - 600 out of 838 < 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 >
Match Document Document Title
6649543 Methods of forming silicon nitride, methods of forming transistor devices, and transistor devices  
The invention encompasses a method of forming silicon nitride on a silicon-oxide-comprising material. The silicon-oxide-comprising material is exposed to activated nitrogen species from a...
6646296 Semiconductor integrated circuit and method for manufacturing the same  
A semiconductor integrated circuit has a MOS transistor formed on an SOI substrate and a subsidiary transistor provided between a body node and a drain node of the MOS transistor and sharing a gate...
6642576 Power semiconductor device having layered structure of power semiconductor elements and terminal members  
An IGBT ( 121 ) and a diode ( 131 ) are joined onto an element arrangement portion ( 111 a ) of a first terminal member ( 111 ) and an element arrangement portion ( 112 a ) of a second terminal...
6642076 Asymmetrical reset transistor with double-diffused source for CMOS image sensor  
A new method to form CMOS image sensors in the manufacture of an integrated circuit device is achieved. The method comprises providing a semiconductor substrate. Sensor diodes are formed in the...
6642577 Semiconductor device including power MOSFET and peripheral device and method for manufacturing the same  
First and second trenches are formed on an n + type substrate at a power MOSFET formation region and a peripheral device formation region, respectively. An n − type epitaxial film, a p type...
6639260 Semiconductor device having a vertical semiconductor element  
A vertical type MOS field effect transistor has a super junction structure between a source electrode and an N + -type drain region. The super junction structure is constituted by a plurality of...
6639273 Silicon carbide n channel MOS semiconductor device and method for manufacturing the same  
A silicon carbide n channel MOS semiconductor device is provided which includes a silicon carbide substrate including a p base region, an n 30 source region and an n + drain region, a gate...
6639279 Semiconductor transistor having interface layer between semiconductor and insulating layers  
The present invention provides a semiconductor device capable of preventing deterioration in carrier mobility of a semiconductor layer, which is a quality of the interface between the semiconductor...
6639278 Semiconductor device  
At one of main surfaces of a silicon substrate serving as an N+type drain region is arranged an N type first high resistance drift layer. On the first high resistance drift layer is arranged an...
6635946 Semiconductor device with trench isolation structure  
A semiconductor device with trench isolation structure is disclosed. The invention uses a trench isolation structure that can be formed by using conventional methods to prevent problems such as...
6633059 Semiconductor device having MOS transistor  
A p type well region, a field insulation film, a gate insulation film, and a gate-use poly-Si layer are formed on the surface of a silicon substrate, after which a laminate of a silicon nitride...
6630699 Transistor device having an isolation structure located under a source region, drain region and channel region and a method of manufacture thereof  
The present invention provides a transistor device that does not experience the problems associated with the prior art transistor devices. The transistor device includes a dielectric region located...
6630700 NMOS circuit in isolated wells that are connected by a bias stack having pluralirty of diode elements  
An integrated NMOS circuit including an active stack having a plurality of isolated p-well active devices M 1 -M 3 , a bias stack having a plurality of diode-connected isolated p-well bias devices...
6627488 Method for fabricating a semiconductor device using a damascene process  
Disclosed herein is a method of fabricating a semiconductor device using a damascene process. The method comprises the steps of: forming a dummy gate electrode on a semiconductor substrate; forming...
6627928 Method of manufacturing an integrated circuit, for integrating an electrically programmable, non-volatile memory and high-performance logic circuitry in the same semiconductor chip  
A method for manufacturing an integrated circuit having a memory device and a logic circuit includes forming a plurality of first transistors in a first portion of a semiconductor substrate, a...
6627973 Void-free interlayer dielectric (ILD0) for 0.18-micron flash memory semiconductor device  
A method of eliminating voids in the interlayer dielectric material of 0.18-μm flash memory semiconductor devices and a semiconductor device formed by the method. The present invention provides a...
6624489 Formation of silicided shallow junctions using implant through metal technology and laser annealing process  
A method for producing MOS type transistors with deep source/drain junctions and thin, silicided contacts with desireable interfacial and electrical properties. The devices are produced by a method...
6624455 Semiconductor device and method of manufacturing the same including drain pinned along channel width  
In a semiconductor device, pining regions 105 are disposed along the junction portion of a drain region 102 and a channel forming region 106 locally in a channel width direction. With this...
6617212 Semiconductor device and method for fabricating the same using damascene process  
A semiconductor device and a method for fabricating the semiconductor device using a damascene process are disclosed. The method includes forming an Al 2 O 3 film over a dummy gate disposed over a...
6617663 Methods of manufacturing semiconductor devices  
A planarization method includes forming a dummy pattern in a film over a substrate. The dummy pattern includes a plurality of concave and convex portions. A chemical-mechanical polishing process is...
6617624 Metal gate electrode stack with a passivating metal nitride layer  
A low resistance gate stack for an integrated circuit transistor is provided including a metal layer having a first width and a metal nitride over surfaces of the metal layer being less than about...
6617625 Solid state imager  
A device region surrounded by a device isolation region has a rectangular shape with a width in a direction in which a gate electrode of a transfer gate extends. A signal accumulation region of a...
6611021 Semiconductor device and the method of manufacturing the same  
A semiconductor device includes an improved drain drift layer structure of alternating conductivity types, that is easy to manufacture, and that facilitates realizing a high current capacity and a...
6611023 Field effect transistor with self alligned double gate and method of forming same  
A fully depleted silicon on insulator (SOI) field effect transistor (FET) includes a gate positioned above a channel region and an aligned back gate positioned below the channel region and the...
6608336 Lateral double diffused MOS transistor  
To reduce ON-state resistance with desired withstand voltage secured, a semiconductor device provided with a gate electrode formed on a semiconductor substrate via a gate insulating film, an LP...
6608352 Determination of thermal resistance for field effect transistor formed in SOI technology  
In a system for determining thermal resistance of a field effect transistor, a p-n junction is formed with one of drain and source regions of the transistor for determining a current versus...
6605498 Semiconductor transistor having a backfilled channel material  
A stressed channel is formed in a PMOS transistor by etching a recess and subsequently backfilling the recess with an epitaxially formed alloy of silicon, germanium, and an n-type dopant. The alloy...
6605846 Shallow junction formation  
A method of forming junctions in a semiconductor substrate, where a gate dielectric layer is grown on the semiconductor substrate, a gate electrode layer is deposited on the gate dielectric layer,...
6603160 MOS capacitor, liquid crystal display, integrated circuit and method of manufacture thereof  
A MOS capacitor used in an active matrix liquid crystal display is manufactured by a process comprising the steps of forming capacitor electrodes with a dielectric layer between them in a...
6603179 Semiconductor apparatus including CMOS circuits and method for fabricating the same  
6600205 Method for making low voltage transistors with increased breakdown voltage to substrate having three different MOS transistors  
A high-breakdown voltage transistor ( 30; 30′ ) is disclosed. The transistor ( 30; 30′ ) is formed into a well arrangement in which a shallow, heavily doped, well ( 44 ) is disposed at least...
6600182 High current field-effect transistor  
A MOSFET that provides high current conduction at high frequency includes a deposited layer over a substrate of a first conductivity type, with source and drain regions adjoining a top surface of...
6590241 MOS transistors with improved gate dielectrics  
The specification describes silicon MOS devices with gate dielectrics having the composition Ta 1−x Al x O y , where x is 0.03-0.7 and y is 1.5-3, Ta 1−x Si x O y , where x is 0.05-0.15, and y...
6589831 Transistor structure using epitaxial layers and manufacturing method thereof  
First and second epitaxial layers are spaced apart from one another over the surface of a semiconductor substrate. A gate electrode is formed over the surface of the substrate, and extends within a...
6590231 Transistor that uses carbon nanotube ring  
A transistor of nanometer size is provided, which is capable of high-speed operation and operates at room temperatures by using carbon nanotubes for semiconductor devices. The transistor uses a...
6586787 Single electron device  
A single electron device. Fabricated from nanoparticle derivatives, particularly from Au and fullerene nanoparticle derivatives, the device reduces thermal fluctuation in the nanoparticle array and...
6580108 Insulated gate bipolar transistor decreasing the gate resistance  
An insulated gate transistor comprising a first semiconductor region, a second semiconductor region includes plural portions, a third semiconductor region, a fourth semiconductor region, a first...
6576939 Semiconductor processing methods, methods of forming electronic components, and transistors  
In one implementation, first and second layers are formed over a substrate. One of the layers has a higher oxidation rate than the other when exposed to an oxidizing atmosphere. The layers...
6570235 Cells array of mask read only memory  
A cells array of mask read only memory, at least includes numerous essentially parallel cells chains and numerous isolation dielectric layers which are located between any two adjacent cells...
6563151 Field effect transistors having gate and sub-gate electrodes that utilize different work function materials and methods of forming same  
Field effect transistors include a semiconductor substrate having a channel region of first conductivity type therein extending adjacent a surface thereof. Source and drain regions of second...
6559489 Semiconductor device and method of manufacturing the same  
A semiconductor device capable of a high-speed operation is provided. The semiconductor device is provided with low concentration impurity regions, a gate electrode formed with gate oxide film...
6552388 Hafnium nitride gate dielectric  
A field effect semiconductor device comprising a high permittivity hafnium (or hafnium-zirconium) nitride gate dielectric and a method of forming the same are disclosed herein. The device comprises...
6552377 Mos transistor with dual metal gate structure  
A method for making a ULSI MOSFET includes depositing a high-k gate insulator on a silicon substrate and then depositing a field oxide layer over the gate insulator. The field oxide layer is masked...
6548842 Field-effect transistor for alleviating short-channel effects  
An IGFET ( 40 or 42 ) has a channel zone ( 64 or 84 ) situated in body material ( 50 ). Short-channel threshold voltage roll-off and punchthrough are alleviated by arranging for the net dopant...
6548864 High density MOS technology power device  
A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a plurality of elementary functional units, a first insulating material layer placed above the...
6548847 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING A FIRST WIRING STRIP EXPOSED THROUGH A CONNECTING HOLE, A TRANSITION-METAL FILM IN THE CONNECTING HOLE AND AN ALUMINUM WIRING STRIP THEREOVER, AND A TRANSITION-METAL NITRIDE FILM BETWEEN THE ALUMINUM WIRING STRIP AND THE TRANSITION-METAL FILM  
Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by...
6548872 Integrated circuitry comprising multiple transistors with different channel lengths  
A method of defining at least two different field effect transistor channel lengths includes forming a channel defining layer over a substrate, the semiconductor substrate having a mean global...
6548875 Sub-tenth micron misfet with source and drain layers formed over source and drains, sloping away from the gate  
A semiconductor device having a low channel resistance without degrading transistor characteristics even for the 0.1 μm generation or later, and also: a manufacturing method of the device. The...
6537921 Vertical metal oxide silicon field effect semiconductor diodes  
The present invention includes methods and apparatus as described in the claims. Briefly, semiconductor diodes having a low forward conduction voltage drop, a low reverse leakage current, a high...
6537843 Thin film transistor and method of manufacturing the same  
A thin film transistor is disclosed, including an insulating substrate, a semiconductor layer formed on the insulating substrate, the semiconductor layer having an active region and an impurity...
Matches 551 - 600 out of 838 < 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 >