Matches 501 - 550 out of 838 < 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 >
Match Document Document Title
6774416 Small area cascode FET structure operating at mm-wave frequencies  
A small area cascode FET structure capable of operating at mm-wave frequenices cascades a common-source (CS) FET with a common gate (CG) FET, in a smaller physical area than conventional cascode...
6774418 Low dielectric silicon oxynitride spacer films and devices incorporating such films  
A method of depositing a silicon oxynitride spacer film on a gate stack in a semiconductor device involves contacting the gate stack with bistertiarybutylaminosilane (BTBAS), at least one nitrogen...
6770951 P-type LDMOS device with buried layer to solve punch-through problems and process for its manufacture  
P-type LDMOS devices have been difficult to integrate with N-type LDMOS devices without adding an extra mask because the former have been unable to achieve the same breakdown voltage as the latter...
6768148 Devices with active areas having increased ion concentrations adjacent to isolation structures  
Active areas of integrated circuits can be formed by implanting first ions into a first active area of a substrate adjacent to an isolation structure in the substrate and between a source and a...
6765249 Thin-film transistors formed on a flexible substrate  
A method for is provided forming a thin-film transistor (TFT) on a flexible substrate. The method comprises: supplying a metal foil substrate such as titanium (Ti), Inconel alloy, stainless steel,...
6765248 Field effect transistor and fabrication method  
A field effect transistor contains a gate stack with a first layer, preferably a polysilicon layer, on a gate oxide disposed on a substrate, and over the first layer, a second layer, preferably a...
6762454 Stacked polysilicon layer for boron penetration inhibition  
A semiconductor device formed on a semiconductor substrate having an active region and a method of making the same is disclosed. The semiconductor device includes a stacked polysilicon layer formed...
6753231 Semiconductor integrated circuit and method for manufacturing the same  
An operational margin of a memory of a semiconductor integrated circuit device including an SRAM is improved. In order to set the Vth of driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load...
6750520 Two-bit semiconductor memory with enhanced carrier trapping  
A nonvolatile semiconductor memory comprises a pair of diffused layers formed in the surface area of a p-type silicon substrate, and a gate electrode (polysilicon film and tungsten silicide film...
6747332 Semiconductor component having high voltage MOSFET and method of manufacture  
A semiconductor component includes a semiconductor substrate ( 310 ) having a first conductivity type, a first semiconductor device ( 320 ) at least in a first portion of the semiconductor...
6747300 H-bridge drive utilizing a pair of high and low side MOSFETs in a common insulation housing  
A fully protected H-bridge for a d-c motor consists of two high side MOSFETs and a control and logic IC on a first conductive heat sink all within a first package and two discrete low side MOSFETs....
6744090 Damascene capacitor formed in metal interconnection layer  
A method for fabricating a semiconductor device that forms a capacitor and metal interconnection in the same level, simultaneously using a damascene process for forming a metal interconnection. A...
6744098 Transistor devices  
The invention encompasses a method of forming silicon nitride on a silicon-oxide-comprising material. The silicon-oxide-comprising material is exposed to activated nitrogen species from a...
6740912 Semiconductor device free of LLD regions  
A reduced feature size MOS transistor and its method of manufacture is disclosed. The present invention reduces short channel effects but does not include an LDD structure In an illustrative...
6740941 Semiconductor device including a gate insulating film made of high-dielectric-constant material  
A metal target, at least the surface region of which has been oxidized, is prepared in a chamber. Then, a sputtering process is performed on the metal target with an inert gas ambient created in...
6740913 MOS transistor using mechanical stress to control short channel effects  
A transistor using mechanical stress to alter carrier mobility. Voids are formed in one or more of the source, drain, channel or gate regions to introduce tensile or compressive stress to improve...
6740911 α-WO3-gate ISFET devices and method of making the same  
Disclosed is an ISFET comprising a H + -sensing membrane consisting of RF-sputtering a-WO 3 . The a-WO 3 /SiO 2 -gate ISFET of the present invention is very sensitive in aqueous solution, and...
6740914 FET circuit block with reduced self-heating  
A field effect transistor (FET) is disclosed that includes a heat spreader adapted to reduce the thermal resistance and channel operating temperature of a field effect transistor used in a circuit...
6737929 Hybrid n&plus and p&plus gate-doped voltage variable capacitors to improve linear tuning range in voltage controlled oscillators  
A method for operating a wide band voltage controlled oscillator comprises using a control voltage to tune the capacitance of at least one hybrid n+ and p+ gate-doped voltage variable capacitor of...
6734488 Semiconductor device and manufacturing method thereof  
A semiconductor device with a capacitor having a charge retaining capability improved by preventing generation of a leakage current in a capacitor dielectric film, and a manufacturing method of the...
6727539 Embedded vertical DRAM arrays with silicided bitline and polysilicon interconnect  
A structure and process for fabricating embedded vertical DRAM cells includes fabricating vertical MOSFET DRAM cells with silicided polysilicon layers in the array regions, the landing pad and/or...
6727534 Electrically programmed MOS transistor source/drain series resistance  
High-speed MOS transistors are provided by forming a conductive layer embedded in transistor gate sidewall spacers. The embedded conductive layer is electrically insulated from the gate electrode...
6724025 MOSFET having high and low dielectric materials  
A semiconductor device comprises a channel of a first conductive type formed on a surface layer of a semiconductor substrate, source and a drain of a second conductive type formed on both sides of...
6720630 Structure and method for MOSFET with metallic gate electrode  
A method of forming a metal oxide semiconductor field effect transistor (MOSFET) having a metallic gate electrode that is protected with hanging sidewall spacers during a subsequent gate oxidation...
6713826 Method for fabricating a semiconductor device having contacts self-aligned with a gate electrode thereof  
A gate electrode is made up of a lower electrode of polysilicon and an upper electrode including a low-resistance film. A nitride sidewall is formed to cover at least the side faces of an insulator...
6713794 Lateral semiconductor device  
A semiconductor device including a semiconductor base, a first semiconductor region formed in the semiconductor base, a second semiconductor region formed in the semiconductor base, a third...
6713790 Semiconductor device and method for fabricating the same  
In the method for fabricating a semiconductor device of the present invention, a collector layer of a first conductivity type is formed in a region of a semiconductor substrate sandwiched by device...
6710383 MISFET semiconductor device having a high dielectric constant insulating film with tapered end portions  
There is provided a semiconductor device configured as follows. On a semiconductor substrate, a titanium oxide film which is an insulating film having a higher dielectric constant than that of a...
6710414 Surface geometry for a MOS-gated device that allows the manufacture of dice having different sizes  
A surface geometry for a MOS-gated device is provided that allows device size to be varied in both the x-axis and the y-axis by predetermined increments. The actual device size is set or...
6707079 Twin MONOS cell fabrication method and array organization  
Presented in this invention is a fabricating method and its array organization for a high-density twin MONOS memory device integrating a twin MONOS memory cell array and CMOS logic device circuit....
6707087 Structure of chalcogenide memory element  
A memory structure that includes a control element electrode, a heater electrode, a memory element electrode, a chalcogenide based memory element disposed between the memory element electrode and...
6700143 Dummy structures that protect circuit elements during polishing  
Circuit elements (e.g. transistor gates) formed over a semiconductor substrate are protected by adjacent dummy structures during mechanical or chemical mechanical polishing of an overlying dielectric.
6700170 Insulated gate transistor having a gate insulator containing nitrogen atoms and fluorine atoms  
An insulated gate transistor in which nitride oxide film having a nitrogen concentration of 1×10 20 (/cm 3 ) or more and containing a halogen element is used as a gate insulator. Because the gate...
6693315 Semiconductor device with an active region and plural dummy regions  
There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing...
6690046 Semiconductor assemblies, methods of forming structures over semiconductor substrates, and methods of forming transistors associated with semiconductor substrates  
The invention encompasses semiconductor assemblies that include a semiconductor substrate having a first region and a second region defined therein. A first oxide region is on the substrate and...
6690047 MIS transistor having a large driving current and method for producing the same  
In a MIS transistor, the top surfaces of source/drain regions (S/D diffusion layers) formed on a semiconductor substrate 1 are arranged nearer to a gate electrode than a channel plane on the...
6686620 FRAM and method of fabricating the same  
A FRAM having a ferroelectric capacitor comprises a cylindrical type bottom electrode. A ferroelectric film is thinly stacked over the bottom electrode, and the first portion of the top electrode...
6682966 Semiconductor device and method for producing the same  
A semiconductor device according to the present invention includes a semiconductor substrate; device isolation regions provided in the semiconductor substrate; a first conductivity type...
6677607 Organic semiconductor device having an oxide layer  
A semiconductor device having a flexible or rigid substrate ( 11 ) having a gate electrode ( 21 ), a source electrode ( 61 and 101 ), and a drain electrode ( 62 and 102 ) formed thereon and...
6674123 MOS control diode and method for manufacturing the same  
A MOS control diode is provided for power switching. In the MOS control diode, a switching speed is high and a reverse leakage current characteristic is improved without additionally needing...
6667506 Variable capacitor with programmability  
Multiple variations of a variable capacitor or varactor 10 with built-in programmability; exhibiting high quality, Q, factors; manufactured in a standard CMOS process in silicon on insulator. The...
6667500 Semiconductor device and method for protecting such device from a reversed drain voltage  
An LDMOS field effect transistor ( 80 ) provides protection against the inadvertent reversal of polarity of voltage applied across the device. To protect an N-channel device, a floating P-type...
6664153 Method to fabricate a single gate with dual work-functions  
A method for forming a single gate having a dual work-function is described. A gate electrode is formed overlying a gate dielectric layer on a substrate. Sidewalls of the gate electrode are...
6664585 Semiconductor memory device having multilayered storage node contact plug and method for fabricating the same  
A semiconductor memory device includes a bit line stack and a storage node contact hole which are aligned at bit line spacers formed at both side walls of the bit line stack and exposes a pad. The...
6661063 Semiconductor integrated circuit device  
Disclosed is a semiconductor integrated circuit device (e.g., an SRAM) having memory cells each of a flip-flop circuit constituted by a pair of drive MISFETs and a pair of load MISFETs, the MISFETs...
6661055 Transistor in semiconductor devices  
The present invention relates to a transistor in a semiconductor device and method of manufacturing the same. According to the present invention, the transistor has an auxiliary electrode to which...
6661044 Method of manufacturing MOSEFT and structure thereof  
A method of manufacturing an MOSFET. A substrate is provided. A trench is formed in the substrate. A sacrificial layer is formed to fill the trench. A doped semiconductive layer is formed over the...
6657267 Semiconductor device and fabrication technique using a high-K liner for spacer etch stop  
A semiconductor device and method of fabrication are disclosed. The semiconductor device includes a liner composed of a high-K material. The liner has a portion separating a sidewall spacer from a...
6657244 Structure and method to reduce silicon substrate consumption and improve gate sheet resistance during silicide formation  
A method of fabricating a semiconductor structure where a low gate resistance is obtained, while simultaneously reducing silicon consumption in the source/drain diffusion regions. The method...
6653674 Vertical source/drain contact semiconductor  
A semiconductor device is provided having angled dopant implantation and vertical trenches in the silicon on insulator substrate adjacent to the sides of a semiconductor gate. A second dopant...
Matches 501 - 550 out of 838 < 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 >