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8975670 Semiconductor device and structure for heat removal  
A semiconductor device, including: a semiconductor substrate with a first layer including first transistors; a shield layer overlaying the first layer; a second layer overlaying the shield layer,...
8933490 Structure, method and system for complementary strain fill for integrated circuit chips  
A structure, method and system for complementary strain fill for integrated circuit chips. The structure includes a first region of an integrated circuit having multiplicity of n-channel and...
8927353 Fin field effect transistor and method of forming the same  
A fin field effect transistor and method of forming the same. The fin field effect transistor includes a semiconductor substrate having a fin structure and between two trenches with top portions...
8912057 Fabrication of nickel free silicide for semiconductor contact metallization  
A semiconductor device with an n-type transistor and a p-type transistor having an active region is provided. The active region further includes two adjacent gate structures. A portion of a...
8866195 III-V compound semiconductor device having metal contacts and method of making the same  
A semiconductor device comprises a semiconductor substrate; a channel layer of at least a first III-V semiconductor compound above the semiconductor substrate; a gate stack structure above a first...
8785987 IGFET device having an RF capability  
An IGFET device includes: —a semiconductor body having a major surface, —a source region of first conductivity type abutting the surface, —a drain region of the first conductivity-type abutting...
8748948 SiC semiconductor device having CJFET and method for manufacturing the same  
A SiC semiconductor device includes: a SiC substrate made of intrinsic SiC having semi-insulating property; first and second conductive type SiC layers disposed in the substrate; an insulation...
8748244 Enhancement and depletion mode GaN HMETs on the same substrate  
The present invention relates to fabrication of enhancement mode and depletion mode High Electron Mobility Field Effect Transistors on the same die separated by as little as 10 nm. The fabrication...
8742475 Field effect transistor device and fabrication  
In one aspect of the present invention, a field effect transistor (FET) device includes a first FET including a dielectric layer disposed on a substrate, a first portion of a first metal layer...
8735239 Semiconductor devices including compressive stress patterns and methods of fabricating the same  
Provided is a method of fabricating a semiconductor device. Gate patterns are formed on a substrate including an NMOS transistor region and a PMOS transistor region. A spacer structure is formed...
8728905 Stress-generating shallow trench isolation structure having dual composition  
A shallow trench isolation structure containing a first shallow trench isolation portion comprising the first shallow trench material and a second shallow trench isolation portion comprising the...
8716764 Semiconductor device and manufacturing method thereof  
A semiconductor device and a manufacturing method thereof are provided. The fin semiconductor device includes a fin formed on a substrate and an insulating material layer formed on the substrate...
8685812 Logic switch and circuits utilizing the switch  
A logic switch intentionally utilizes GIDL current as its primary mechanism of operation. Voltages may be applied to a doped gate overlying and insulated from a pn junction. A first voltage...
8558318 Integration scheme for changing crystal orientation in hybrid orientation technology (HOT) using direct silicon bonded (DSB) substrates  
Optimizing carrier mobilities in MOS transistors in CMOS ICs requires forming (100)-oriented silicon regions for NMOS and (110) regions for PMOS. Methods such as amorphization and templated...
8481372 JFET device structures and methods for fabricating the same  
In accordance with the present techniques, there is provided a JFET device structures and methods for fabricating the same. Specifically, there is provided a transistor including a semiconductor...
8476678 CMOS Transistor with dual high-k gate dielectric  
A CMOS device with transistors having different gate dielectric materials and a method of manufacture thereof. A CMOS device is formed on a workpiece having a first region and a second region. A...
8470674 Structure, method and system for complementary strain fill for integrated circuit chips  
A structure, method and system for complementary strain fill for integrated circuit chips. The structure includes a first region of an integrated circuit having multiplicity of n-channel and...
8466451 Single gate inverter nanowire mesh  
A FET inverter is provided that includes a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels,...
8466502 Metal-gate CMOS device  
A method for fabricating a metal-gate CMOS device. A substrate having thereon a first region and a second region is provided. A first dummy gate structure and a second dummy gate structure are...
8455946 Lateral stack-type super junction power semiconductor device  
A lateral stack-type super junction power semiconductor device includes a semiconductor substrate; an epitaxial stack structure on the semiconductor substrate, having a first epitaxial layer and a...
8441047 Semiconductor device and method for manufacturing the same  
An object is to provide an n-channel transistor and a p-channel transistor having a preferred structure using an oxide semiconductor. A first source or drain electrode which is electrically...
8435841 Enhancement of ultraviolet curing of tensile stress liner using reflective materials  
A method of manufacturing a semiconductor device begins by fabricating an n-type metal oxide semiconductor (NMOS) transistor structure on a semiconductor wafer. The method continues by forming an...
8415720 Vertically pinched junction field effect transistor  
A vertical junction field-effect transistor in a CMOS base-technology. The vertical junction field-effect transistor includes a semiconductor substrate having a source region and a drain region, a...
RE43945 Wiring layout of semiconductor device and design method of the same  
A semiconductor device is the semiconductor device which includes more than one field effect transistor having a gate electrode to which an electrical interconnect wire is connected and a gate...
8329521 Method and device with gate structure formed over the recessed top portion of the isolation structure  
A method includes providing a substrate having a first surface, forming an isolation structure disposed partly in the substrate and having an second surface higher than the first surface by a step...
8329568 Semiconductor device and method for making the same  
In one embodiment of the present invention, a field effect transistor device is provided. The field effect transistor device comprises an active area, including a first semiconductor material of a...
8304780 Printed dopant layers  
A method for making an electronic device, such as a MOS transistor, including the steps of forming a plurality of semiconductor islands on an electrically functional substrate, printing a first...
8299530 Structure and method to fabricate pFETS with superior GIDL by localizing workfunction  
A semiconductor structure and a method of forming the same are provided in which the gate induced drain leakage is controlled by introducing a workfunction tuning species within selected portions...
8268688 Production of VDMOS-transistors having optimized gate contact  
A method for producing VDMOS transistors in which a specific layer arrangement and a specific method sequence allow setting up an improved gate contact when simultaneously producing source and...
8236475 Methods for removing a photoresist from a metal-comprising material  
Methods for removing a photoresist from a metal-comprising material are provided. In accordance with an exemplary embodiment of the present invention, the method comprises applying to the...
8183605 Reducing transistor junction capacitance by recessing drain and source regions  
By recessing portions of the drain and source areas on the basis of a spacer structure, the subsequent implantation process for forming the deep drain and source regions may result in a moderately...
8178902 CMOS transistor with dual high-k gate dielectric and method of manufacture thereof  
A CMOS device with transistors having different gate dielectric materials and a method of manufacture thereof. A CMOS device is formed on a workpiece having a first region and a second region. A...
8178872 Molecular device, imaging device, photosensor, and electronic apparatus  
A molecular device includes a gold electrode, cytochrome c552 or a derivative or variant thereof immobilized on the gold electrode, and an electron transfer protein coupled to the cytochrome c552...
8084308 Single gate inverter nanowire mesh  
Nanowire-based devices are provided. In one aspect, a field-effect transistor (FET) inverter is provided. The FET inverter includes a plurality of device layers oriented vertically in a stack,...
8063450 Assembly of nanoscaled field effect transistors  
The present invention relates to vertical nanowire transistors with a wrap-gated geometry. The threshold voltage of the vertical nanowire transistors is controlled by the diameter of the nanowire,...
8035168 Elevation of transistor channels to reduce impact of shallow trench isolation on transistor performance  
Roughly described, transistor channel regions are elevated over the level of certain adjacent STI regions. Preferably the STI regions that are transversely adjacent to the diffusion regions are...
8013395 Semiconductor device and method for fabricating the same  
The distance between a substrate contact portion and an active region in a p-type MIS transistor is greater than the distance between a substrate contact portion and an active region in an n-type...
8008731 IGFET device having a RF capability  
An IGFET device includes: —a semiconductor body (2) having a major surface, —a source region (3) of first conductivity type abutting the surface, —a drain region (6,7) of the first...
7989283 Manufacturing method of semiconductor device  
A manufacturing method of a semiconductor device is provided for improving the reliability of a semiconductor device including a MISFET with a high dielectric constant gate insulator and a metal...
7973344 Double gate JFET with reduced area consumption and fabrication method therefor  
Double gate JFET with reduced area consumption and fabrication method therefore. Double-gate semiconductor device including a substrate having a shallow trench isolator region comprising a first...
7943456 Selective wet etch process for CMOS ICs having embedded strain inducing regions and integrated circuits therefrom  
A method for fabricating a CMOS integrated circuit (IC) and ICs therefrom includes providing a substrate having a semiconductor surface including PMOS regions for PMOS devices and NMOS regions for...
7893437 Semiconductor device and manufacturing method thereof  
A semiconductor device and method of manufacturing the same are disclosed. An example semiconductor device includes a semiconductor substrate having a first well, a first source electrode, a drain...
7855404 Bipolar complementary semiconductor device  
A complementary BiCMOS semiconductor device comprises a substrate of a first conductivity type and a number of active regions which are provided therein and which are delimited in the lateral...
7829926 Demultiplexers using transistors for accessing memory cell arrays  
A demultiplexer using transistors for accessing memory cell arrays. The demultiplexer includes (a) a substrate; (b) 2N semiconductor regions which are parallel to one another and run in a first...
7821072 Semiconductor device comprising a stress applying insulating film  
In a semiconductor device, a transistor in an N-type logic region NL is covered with a tensile stress applying film and a transistor in a P-type logic region PL is covered with a compressive...
7821138 Semiconductor device with an improved operating property  
The semiconductor comprises an n-channel transistor forming region and a p-channel transistor forming region, which are disposed while being sectioned by an element isolation region. The stress...
7781276 Methods of forming CMOS integrated circuits that utilize insulating layers with high stress characteristics to improve NMOS and PMOS transistor carrier mobilities  
A CMOS integrated circuit has NMOS and PMOS transistors therein and an insulating layer extending on the NMOS transistors. The insulating layer is provided to impart a relatively large tensile...
7781809 High voltage depletion layer field effect transistor  
In a high voltage junction field effect transistor, a first well (11) of a first conductivity type is formed in a substrate (10) of a second conductivity type. A source (14) and a drain (15) which...
7763510 Method for PFET enhancement  
A semiconductor process and apparatus includes forming PMOS transistors (90) with enhanced hole mobility in the channel region by forming a hydrogen-rich silicon nitride layer (91, 136) on or...
7754555 Transistor having a channel with biaxial strain induced by silicon/germanium in the gate electrode  
By forming a stressed semiconductor material in a gate electrode, a biaxial tensile strain may be induced in the channel region, thereby significantly increasing the charge carrier mobility. This...
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