|
Match
|
Document |
Document Title |
|
|
8178942 |
Electrically alterable circuit for use in an integrated circuit device
An electrically alterable circuit (EAC), suitable for use in an integrated circuit, includes a first interconnect, a link element, and a second interconnect. A first set of interconnect vias...
|
|
|
8178906 |
Laser chalcogenide phase change device
A laser activated phase change device for use in an integrated circuit comprises a chalcogenide fuse configured to connect a first patterned metal line and a second patterned metal line and...
|
|
|
8178944 |
Method for forming a one-time programmable metal fuse and related structure
According to one exemplary embodiment, a method for forming a one-time programmable metal fuse structure includes forming a metal fuse structure over a substrate, the metal fuse structure including...
|
|
|
8163640 |
Metal gate compatible electrical fuse
A dielectric material layer is formed on a metal gate layer for a metal gate electrode, and then lithographically patterned to form a dielectric material portion, followed by formation of a...
|
|
|
8164120 |
Semiconductor device with capacitor and fuse and its manufacture
An upper electrode of a capacitor has a two-layer structure of first and second upper electrodes. A gate electrode of a MOS field effect transistor and a fuse are formed by patterning conductive...
|
|
|
8159041 |
Semiconductor device and manufacturing method thereof
A semiconductor device includes: a lower layer interconnection formed on a chip; an upper layer interconnection formed in an upper layer above the lower layer interconnection above the chip; an...
|
|
|
8143692 |
Capacitance trimming circuit of semiconductor device having vertically stacked capacitor layers and operation method thereof
A capacitance trimming circuit of a semiconductor device may include a plurality of capacitor layers and/or a plurality of fuses. The plurality of capacitor layers may be vertically stacked. The...
|
|
|
8134187 |
Integrated mask-programmable logic devices with multiple metal levels and manufacturing process thereof
Integrated mask-programmable device, having a plurality of metal levels including a top metal level, a bottom metal level and a first intermediate metal level formed between the top and bottom...
|
|
|
8134220 |
Two-terminal nanotube devices including a nanotube bridge and methods of making same
Nanotube switching devices having nanotube bridges are disclosed. Two-terminal nanotube switches include conductive terminals extending up from a substrate and defining a void in the substrate....
|
|
|
8129709 |
Nonvolatile memory device
A nonvolatile memory device (21) is provided with a semiconductor substrate, a plurality of active regions (3) formed on the semiconductor substrate and extending in a band, a plurality of select...
|
|
|
8124971 |
Implementation of diffusion barrier in 3D memory
One or more diffusion barriers are formed around one or more conductors in a three dimensional or 3D memory cell. The diffusion barriers allow the conductors to comprise very low resistivity...
|
|
|
8120007 |
Phase-change memory device, phase-change channel transistor and memory cell array
A phase-change channel transistor includes a first electrode; a second electrode; a memory layer provided between the first and second electrodes; and a third electrode provided for the memory...
|
|
|
8114719 |
Memory device and manufacturing method of the same
An easy-to-use and inexpensive memory device is provided while maintaining product specifications and productivity even when a memory is formed on the same substrate as other functional circuits....
|
|
|
8102019 |
Electrically programmable diffusion fuse
A fuse structure for a semiconductor integrated circuit (IC) includes an anode comprising conductive material overlaying a diffusion material disposed within a substrate layer of the IC, wherein...
|
|
|
8102018 |
Nonvolatile resistive memories having scalable two-terminal nanotube switches
A non-volatile resistive memory is provided. The memory includes at least one non-volatile memory cell and selection circuitry. Each memory cell has a two-terminal nanotube switching device having...
|
|
|
8101977 |
Ballasted polycrystalline fuse
A polycrystalline fuse includes a first layer of polycrystalline material on a substrate and a second layer of a silicide material on the first layer. The first and second layers are shaped to form...
|
|
|
8101976 |
Device selection circuitry constructed with nanotube ribbon technology
A memory system having electromechanical memory cells and decoders is disclosed. A decoder circuit selects at least one of the memory cells of an array of such cells. Each cell in the array is a...
|
|
|
8089105 |
Fuse link structures using film stress for programming and methods of manufacture
A method of forming a programmable fuse structure includes forming at least one shallow trench isolation (STI) in a substrate, fanning an e-fuse over the at least one STI and depositing an...
|
|
|
8080861 |
Semiconductor device
A semiconductor device includes an electric fuse and first and second large area wirings for applying a voltage to the electric fuse. The electric fuse includes a fuse unit which includes an...
|
|
|
8076760 |
Semiconductor fuse arrangements
The invention includes semiconductor fuse arrangements containing an electrically conductive plate over and in electrical contact with a plurality of electrically conductive links. Each of the...
|
|
|
8076751 |
Circuit protection device including resistor and fuse element
An integral circuit protection device includes a substrate disposed between first and second terminals. The substrate is composed of a resistive material. A first conductive layer is disposed on a...
|
|
|
8076673 |
Recessed gate dielectric antifuse
A recessed dielectric antifuse device includes a substrate and laterally spaced source and drain regions formed in the substrate. A recess is formed between the source and drain regions. A gate and...
|
|
|
8063454 |
Semiconductor structures including a movable switching element and systems including same
Semiconductor structures including a movable switching element having a base disposed on a conductive pad, a body extending from the base, and an end laterally adjacent and spaced apart from a...
|
|
|
8058702 |
Phase change memory cell
A phase change memory cell is disclosed, including a first electrode and a second electrode, and a plurality of recording layers disposed between the first and second electrodes. The phase of an...
|
|
|
8053863 |
Electrical fuse and semiconductor device
An electrical fuse comprises: an interconnect to be cut; and a first terminal and a second terminal which are respectively provided at both ends of the interconnect to be cut. The interconnect to...
|
|
|
8053346 |
Semiconductor device and method of forming gate and metal line thereof with dummy pattern and auxiliary pattern
A gate in a semiconductor device is formed to have a dummy gate pattern that protects a gate. Metal lines are formed to supply power for a semiconductor device and transfer a signal. A...
|
|
|
8044489 |
Semiconductor device with fluorine-containing interlayer dielectric film to prevent chalcogenide material layer from exfoliating from the interlayer dielectric film and process for producing the same
A semiconductor device having a phase-change memory cell comprises an interlayer dielectric film formed of, for example, SiOF formed on a select transistor formed on a main surface of a...
|
|
|
8044395 |
Semiconductor memory apparatus for controlling pads and multi-chip package having the same
A semiconductor memory apparatus includes a first pad group located along a first edge of a plurality of banks, a second pad group located along a second edge of the plurality of banks opposite the...
|
|
|
8044490 |
Semiconductor device including fuse
Provided is a semiconductor device including a fuse, in which a insulating layer surrounding the fuse or metal wiring is prevented from being damaged due to the cut of a fuse, which can occur when...
|
|
|
8031506 |
One-time programmable memory cell
A disclosed embodiment is a programmable memory cell having improved IV characteristics comprising a thick oxide spacer transistor interposed between a programmable thin oxide antifuse and a thick...
|
|
|
8030733 |
Copper-compatible fuse target
A copper-compatible fuse target is fabricated by forming a copper target structure at the same time that the copper traces are formed. After the copper target structure and the copper traces have...
|
|
|
8022443 |
Memory and interconnect design in fine pitch
An integrated circuit includes a plurality of signal lines. A first signal line layer includes a plurality of first signal lines. A second signal line layer includes a plurality of second signal...
|
|
|
8017454 |
Fuse of semiconductor device and method for forming the same
A method for forming a fuse of a semiconductor device includes performing an ion-implanting process at sides of a fuse blowing region of a metal fuse, thereby increasing the concentration of...
|
|
|
8013422 |
Fuse corner pad for an integrated circuit
A fuse corner pad is part of an integrated circuit that includes a built-in fuse contact and a plurality of auxiliary pads. The fuse contact is a conductive metallic or metalloid structure that is...
|
|
|
8008745 |
Latch circuits and operation circuits having scalable nonvolatile nanotube switches as electronic fuse replacement elements
A non-volatile latch circuit is provided. The non-volatile latch circuit includes a nanotube switching element capable of switching between resistance states and non-volatilely retaining the...
|
|
|
7998798 |
Method of cutting electrical fuse
A method of cutting an electrical fuse including a first conductor and a second conductor, the first conductor including a first cutting target region, the second conductor branched from the first...
|
|
|
7994544 |
Semiconductor device having a fuse element
A portion-to-be-melted of a fuse is surrounded by plates, so that heat to be generated in a meltdown portion of the fuse under current supply can be confined or accumulated in the vicinity of the...
|
|
|
7989914 |
Anti-fuse cell and its manufacturing process
An anti-fuse cell includes a standard MOS transistor of an integrated circuit, with source and drain regions covered with a metal silicide layer and at least one track of a resistive layer at least...
|
|
|
7989913 |
Semiconductor device and method for cutting electric fuse
An electric fuse includes: a first interconnect and a second interconnect, formed on a semiconductor substrate; a fuse link, formed on the semiconductor substrate and provided so that an end...
|
|
|
7986163 |
Scalable non-blocking switching network for programmable logic
A scalable non-blocking switching network (SN) having switches and intermediate (stages of) conductors that are used to connect a first plurality of conductors to other multiple sets of conductors...
|
|
|
7986025 |
Semiconductor device and method for manufacturing same
When a metal cap film is provided on an electric fuse, the break-ability of the electric fuse is reduced. A semiconductor device 1 includes interconnects 10, an electric fuse 20 and metal cap films...
|
|
|
7985989 |
Stacked bit line dual word line nonvolatile memory
An arrangement of nonvolatile memory devices, having at least one memory device level stacked level by level above a semiconductor substrate, each memory level comprising an oxide layer...
|
|
|
7982245 |
Circuit with fuse/anti-fuse transistor with selectively damaged gate insulating layer
A semiconductor integrated circuit is disclosed which includes a main transistor and at least one of a fuse transistor or an anti-fuse transistor (“fuse/anti-fuse transistor”). Each transistor typ...
|
|
|
7982285 |
Antifuse structure having an integrated heating element
The present invention provides antifuse structures having an integrated heating element and methods of programming the same, the antifuse structures comprising first and second conductors and a...
|
|
|
7977164 |
Fuse of a semiconductor memory device and repair process for the same
Disclosed herein is a fuse of a semiconductor memory device and a repair process for the same. The fuse includes a lower conductive film of a multilayer interconnection formed on a lower structure...
|
|
|
7973341 |
Fuse of semiconductor device
A method for manufacturing a fuse of a semiconductor device comprises forming an island-type metal fuse in a region where a laser is irradiated, so that laser energy may not be dispersed in a fuse...
|
|
|
7960767 |
System for programmable gate array with sensor array
The present invention provides providing a substrate, forming a sensor array on the substrate, forming a structured array of uncommitted logic surrounding the sensor array on the substrate, and...
|
|
|
7960760 |
Electrically programmable fuse
A semiconductor device includes a fin-fuse and an SOI transistor. The SOI transistor is located on an SOI substrate and has a source region and a drain region. The fin-fuse is connected to one of...
|
|
|
7956385 |
Circuit for protecting a transistor during the manufacture of an integrated circuit device
A circuit for protecting a transistor during the manufacture of an integrated circuit device is disclosed. The circuit comprises a transistor having a gate formed over an active region formed in a...
|
|
|
7956466 |
Structure for interconnect structure containing various capping materials for electrical fuse and other related applications
A design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect...
|