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7423324 Double-gate MOS transistor, double-gate CMOS transistor, and method for manufacturing the same  
In a double-gate MOS transistor, a substrate, an insulating layer, and a semiconductor layer are formed or laminated in that order, an opening extending to the insulating layer is formed in the...
7422945 Cell based integrated circuit and unit cell architecture therefor  
In a unit cell, a first conductive type active region and a second conductive type active region are provided. Those two active regions extend in a first direction. Each of the active regions have...
7402851 Phase changeable memory devices including nitrogen and/or silicon and methods for fabricating the same  
Phase-changeable memory devices and method of fabricating phase-changeable memory devices are provided that include a phase-changeable material pattern of a phase-changeable material that may...
7402847 Programmable logic circuit and method of using same  
A programmable logic circuit, including programmable memory element, suitable for microprocessor applications, and a method of using the circuit are disclosed. The programmable circuit includes at...
7402846 Electrostatic discharge (ESD) protection structure and a circuit using the same  
An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure includes an active device. The active device includes a plurality of drains. Each of the drains has...
7399675 Electronic device including an array and process for forming the same  
An electronic device can include an NVM array, wherein portions of word lines are formed within trenches. Insulating features are formed over heavily doped regions within the substrate. In one...
7394156 Semiconductor integrated circuit device and method of producing the same  
A semiconductor integrated circuit device has a plurality of CMOS-type base cells arranged on a semiconductor substrate and m wiring layers, and gate array type logic cells are composed of the base...
7394115 Semiconductor integrated circuit device having clock signal transmission line and wiring method thereof  
A clock signal transmission line in the semiconductor integrated circuit device includes a plurality of straight portions arranged side by side in a predetermined direction and a plurality of bent...
7385249 Transistor structure and integrated circuit  
A process for forming a conductive gate structure for a sub-0.25 MOSFET technology, has been developed. The process features a conductive gate structure defined from a composite polysilicon or...
7385233 Gate array integrated circuit including a unit cell basic layer having gate terminal regions allowing two contact pads to be disposed laterally  
A gate array integrated circuit forming part of a semiconductor integrated circuit includes a basic layer of a unit cell in which a PMOS and an NMOS transistor are connected with a poly-silicon...
7382155 Enhanced field programmable gate array  
An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same...
7379319 Semiconductor integrated circuit device  
A semiconductor integrated circuit device includes a semiconductor substrate and a plurality of cell transistors provided on a surface of the semiconductor substrate. A local bit line is provided...
7372155 Top layers of metal for high performance IC's  
A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a...
7368787 Fin field effect transistors (FinFETs) and methods for making the same  
In a first aspect, a first method is provided for semiconductor device manufacturing. The first method includes the steps of (1) forming a first side of a fin of a fin field effect transistor...
7368767 Semiconductor integrated circuit device formed by automatic layout wiring by use of standard cells and design method of fixing its well potential  
A standard cell is read from a library and automatic layout wiring is performed, thereby configuring a circuit. Next, each cell column in the configured circuit is searched for an empty region. In...
7365377 Semiconductor integrated circuit device using four-terminal transistors  
In a semiconductor substrate of a first conductivity type, a first well region of the first conductivity type, second well regions of a second conductivity type, and a third well region of the...
7358547 Selective deposition to improve selectivity and structures formed thereby  
Methods and associated apparatus of forming a microelectronic structure are described. Those methods comprise providing a substrate comprising a region of higher active area density comprising...
7355217 MOS transistor structure with easy access to all nodes  
A transistor device structured such that the bulk, gate, drain, and source are all accessible from all four edges of the device is provided. The transistor is created with a four-metal CMOS...
7354847 Method of trimming technology  
A process for trimming a photoresist layer during the fabrication of a gate electrode in a MOSFET is described. A bilayer stack with a top photoresist layer on a thicker organic underlayer is...
7348640 Memory device  
A memory capable of reducing the memory cell size is provided. In this memory, a first gate electrode of a first selection transistor and a second gate electrode of a second selection transistor...
7348612 Metal-semiconductor field effect transistors (MESFETs) having drains coupled to the substrate and methods of fabricating the same  
The present invention provides a unit cell of a metal-semiconductor field-effect transistor (MESFET). The unit cell of the MESFET includes a MESFET having a source region, a drain region and a gate...
7345929 Semiconductor memory device and defect remedying method thereof  
A semiconductor memory device formed on a semiconductor chip includes first memory arrays, a plurality of second memory arrays, a first voltage generator, and first bonding pads. The semiconductor...
7335946 Structures of and methods of fabricating trench-gated MIS devices  
In a trench-gated MIS device contact is made to the gate within the trench, thereby eliminating the need to have the gate material, typically polysilicon, extend outside of the trench. This avoids...
7332753 Semiconductor device, wafer and method of designing and manufacturing the same  
A process margin of an interconnect is to be expanded, to minimize the impact of vibration generated during a scanning motion of a scanning type exposure equipment. In a semiconductor device, the...
7332433 Methods of modulating the work functions of film layers  
Methods for fabricating two metal gate stacks with varying work functions for complementary metal oxide semiconductor (CMOS) devices are provided A first metal layer may be deposited onto a gate...
7332378 Integrated circuit memory system with dummy active region  
An integrated circuit memory system including a substrate formed with equidistant spaced shallow trench isolation regions. Forming active regions and dummy active regions within the substrate...
7330369 NANO-electronic memory array  
Systems and methods are disclosed to process a semiconductor substrate by fabricating a first layer on the substrate using semiconductor fabrication techniques; fabricating a second layer above the...
7326634 Bulk non-planar transistor having strained enhanced mobility and methods of fabrication  
A method of a bulk tri-gate transistor having stained enhanced mobility and its method of fabrication. The present invention is a nonplanar transistor having a strained enhanced mobility and its...
7323726 Method and apparatus for coupling to a common line in an array  
A method and apparatus for coupling to a common line in an array. Gate structures of an integrated circuit are formed. Source and drain regions adjacent to the gate structures are implanted. A...
7323718 Input display with embedded photo sensor  
A readout pixel of an input display is provided. The readout pixel includes the fundamental elements as the normal pixel, and further includes a photo sensing element with a second switching...
7321139 Transistor layout for standard cell with optimized mechanical stress effect  
A layout for a transistor in a standard cell is disclosed. The layout for a transistor includes an active region with at least one portion having a first edge and at least one portion having a...
7321135 Flat panel display  
The claimed invention is directed to a flat panel display having R, G, and B unit pixels. At least one of the R, G, and B unit pixels includes at least two or more transistors, each having source...
7319253 Integrated circuit structures for increasing resistance to single event upset  
A configuration memory cell (“CRAM”) for a field programmable gate array (“FPGA”) integrated circuit (“IC”) device is given increased resistance to single event upset (“SEU”). A...
7307294 Circuit layout structure  
Main-transistors M 1 and M 2 are divided into sub-transistors that are arrayed in a matrix with four rows and four columns to form four cells so that each of the cells is formed of four of the...
7304352 Alignment insensitive D-cache cell  
A D-Cache SRAM cell having a modified design in schematic and layout that exhibits increased symmetry from the circuit schematic and the physical cell layout perspectives. That is, the SRAM cell...
7301182 Circuit layout for improved performance while preserving or improving density  
In one embodiment, a circuit may be formed by forming at least one bent-gate output stage transistor and at least one bent-gate input stage transistor. The bent-gate output stage transistor may be...
7253522 Integrated capacitor for RF applications with Ta adhesion layer  
A precision RF passive component including: a silicon substrate; a first dielectric layer deposited above the silicon substrate; a first metal layer formed above the first dielectric layer; a...
7250644 Electronic device and method for designing the same  
The electronic device includes a plurality of layout regions each including a plurality of patterns defined by a buried structure buried in a substrate. For each of the layout regions, in each of...
7244975 High-voltage device structure  
A high-voltage device structure includes a high-voltage device disposed on a semiconductor substrate. The semiconductor includes an active region and an isolation region, and the high-voltage...
7233032 SRAM device having high aspect ratio cell boundary  
A static random access memory (SRAM) device including a substrate and an SRAM unit cell. The substrate includes an n-doped region interposing first and second p-doped regions. The SRAM unit cell...
7227202 Semiconductor device and cell  
A cell 100 includes three wiring layers (a gate electrode layer, a source/drain electrode layer and a terminal layer) on a semiconductor substrate including transistors formed thereon. One of the...
7217966 Self-protecting transistor array  
A transistor array is self-protected from an electrostatic discharge (ESD) event which can cause localized ESD damage by integrating an ESD protection device into the transistor array. The ESD...
7217964 Method and apparatus for coupling to a source line in a memory device  
A method and apparatus for coupling to a source line. Specifically, embodiments of the present invention disclose a memory device comprising an array of flash memory cells with a source line...
7217962 Wire mesh patterns for semiconductor devices  
Different patterns of interconnects for connecting wells in a semiconductor device are described. For example, a semiconductor device may include n-wells and p-wells arrayed in rows and columns...
7211840 Transistor  
A transistor and a semiconductor integrated circuit with a reduced layout area. Area reduction of a transistor is realized by arranging contacts at higher density. Specifically, in a transistor...
7208780 Semiconductor storage device  
A semiconductor storage device includes a semiconductor substrate; an sulating layer formed on the semiconductor substrate; a first semiconductor layer formed on the insulating layer and insulated...
7205194 Method of fabricating a flash memory cell  
A method of fabricating a flash memory cell having a split gate structure. A sacrificial layer is formed on a floating gate layer formed on a semiconductor substrate. The sacrificial layer is...
7195723 Colloidal solutions and nanocomposites of electrides and alkalides and methods of use  
A colloidal solution and/or nanocomposite having enhanced energy transfer between thermal, electron, phonons, and photons energy states. The composition comprises a synergistic blend of electrides...
7186999 Error reduction circuit for chalcogenide devices  
An error reduction circuit for use in arrays of chalcogenide memory and computing devices. The error reduction circuit reduces the error associated with the output response of chalcogenide devices....
7183594 Configurable gate array cell with extended poly gate terminal  
A configurable gate array cell contains at least two doping zones of a different conduction type and a poly gate terminal. In a plan view representation of the gate array cell, the poly gate...
Matches 1 - 50 out of 382 1 2 3 4 5 6 7 8 >