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7630227 Nano-electronic memory array  
Systems and methods are disclosed to process a semiconductor substrate by fabricating a first layer on the substrate using semiconductor fabrication techniques; fabricating a second layer above the...
7615206 Methods of fabricating nanoscale-to-microscale structures  
Methods for the production of shaped nanoscale-to-microscale structures, wherein a nanoscale-to-microscale template is provided having an original chemical composition and an original shape, and...
7605436 Manufacture of semiconductor device having insulation film of high dielectric constant  
A method contains the steps of (a) heating a silicon substrate in a reaction chamber; and (b) supplying film-forming gas containing source gas, nitridizing gas, and nitridation enhancing gas to a...
7598570 Semiconductor device, SRAM and manufacturing method of semiconductor device  
A semiconductor device according to the present invention is provided with an SOI substrate, an active region, a first insulating film (complete separation insulating film), a second insulating...
7592710 Bond pad structure for wire bonding  
A bond pad structure of an integrated circuit is provided. The bond pad structure includes a conductive bond pad, a first dielectric layer underlying the bond pad, and an M top plate located in...
7589367 Layout structure in semiconductor memory device comprising global work lines, local work lines, global bit lines and local bit lines  
A line layout structure and method in a semiconductor memory device having a hierarchical structure are provided. In a semiconductor memory device having a global word line and a local word line,...
7586132 Power FET with low on-resistance using merged metal layers  
In one embodiment, relatively thin but wide metal bus strips overlying a high power FET are formed to conduct current to the source and drain narrow metal strips. A passivation layer is formed over...
7586131 Transistor array and active-matrix substrate  
A transistor array includes conductor lines, function lines, and transistors. Each of the conductor lines includes a core and a conductor layer that covers the core. Each of the function lines...
7582548 Semiconductor device and manufacturing method thereof  
A semiconductor device is provided. The semiconductor device includes a first gate line, a second gate line, a first contact electrode, first dummy gates, a second gate pad, and a second contact...
7582921 Semiconductor device and method for patterning  
In a masking pattern (a) for patterning word and data lines, length is changed between adjacent word lines so as to be shifted from each other at their tips, and furthermore, the tip of each word...
7573087 Interconnect line selectively isolated from an underlying contact plug  
A means for selectively electrically connecting an electrical interconnect line, such as a bit line of a memory cell, with an associated contact stud and electrically isolating the interconnect...
7566902 Light-emitting device and electronic device  
The present invention provides a light-emitting device that can independently display images of both front and back sides, in a light emitting device that can display in the both sides and also...
7553708 Fabricating method for a liquid crystal display of horizontal electric field applying type  
A liquid crystal display having an applied horizontal electric field comprising: a gate line; a common line substantially parallel to the gate line; a data line arranged to cross the gate line and...
7550790 D/A conversion circuit and semiconductor device  
A D/A conversion circuit with a small area is provided. In the D/A conversion circuit, according to a digital signal transmitted from address lines of an address decoder, one of four gradation...
7538368 Standard cell, standard cell library, and semiconductor integrated circuit with suppressed variation in characteristics  
In a standard cell, at least one of transistors on either side of a transistor having gate length different from that of the other transistors are set to be always in the OFF state. This prevents...
7528455 Narrow width metal oxide semiconductor transistor  
Disclosed is a semiconductor transistor for enhancing performance of PMOS and NMOS transistors, particularly current driving performance, while reducing a narrow width effect. A narrow width MOS...
7522405 High current electrical switch and method  
A method and system are disclosed for a high current electrical switch. The switch may be suitable for switching, rectifying or blocking direct current in the range of one to a thousand amperes per...
7521962 Semiconductor integrated circuit apparatus  
A semiconductor integrated circuit apparatus relates to a structured ASIC that wires functional cells in a common wiring layer, which is not dependent on a user circuit and common to several sorts,...
7514728 Semiconductor integrated circuit device using four-terminal transistors  
In a semiconductor substrate of a first conductivity type, a first well region of the first conductivity type, second well regions of a second conductivity type, and a third well region of the...
7514796 Semiconductor chip capable of being laminated and a semiconductor device including the lamination of a plurality of semiconductor chips  
To prevent short-circuit due to contact of bonding wires each other and to make a semiconductor device compact. A semiconductor chip with a rectangular main surface may comprise: a first side...
7511345 Bulk resistance control technique  
The present invention provides a MOS transistor device for providing ESD protection including at least one interleaved finger having a source, drain and gate region formed over a channel region...
7501672 Method and structure for a self-aligned silicided word line and polysilicon plug during the formation of a semiconductor device  
A method used to form a semiconductor device provides a silicide layer on a plurality of transistor word lines and on a plurality of conductive plugs. In one embodiment, the word lines, one or more...
7501316 Asymmetric memory cell  
Some embodiments provide a memory cell that includes a body region, a source region and a drain region. The body region is doped with charge carriers of a first type, the source region is disposed...
7488657 Method and system for forming straight word lines in a flash memory array  
Embodiments of the present invention disclose a memory device having an array of flash memory cells with source contacts that facilitate straight word lines, and a method for producing the same....
7482644 Integrated semiconductor memory and method for electrically stressing an integrated semiconductor memory  
Semiconductor memories ( 1 ) have segmented word lines ( 5 a, 5 b ), which in each case have a main word line ( 10 a, 10 b ) made of a conductive metal and a plurality of interconnect segments (...
7482670 Enhancing strained device performance by use of multi narrow section layout  
A semiconductor device having high tensile stress. The semiconductor device comprises a substrate having a source region and a drain region. Each of the source region and the drain region includes...
7482630 NAND memory arrays  
A NAND memory array has a substrate, a source select gate formed on the substrate, and a drain select gate formed on the substrate. A string of floating-gate memory cells is formed on the substrate...
7476945 Memory having reduced memory cell size  
A memory capable of reducing the memory cell size is provided. This memory includes a first conductive type first impurity region formed on a memory cell array region of the main surface of a...
7468551 Multiple chips bonded to packaging structure with low noise and multiple selectable functions  
A chip package for semiconductor chips is provided by the method of forming a chip package includes the steps of forming a printed circuit board with a window therethrough; forming semiconductor...
7468296 Thin film germanium diode with low reverse breakdown  
In fabricating an electronic structure, a substrate is provided, and a first barrier layer is provided on the substrate. A germanium thin film diode is provided on the first barrier layer, and a...
7465971 Integrated circuit structures for increasing resistance to single event upset  
A configuration memory cell (“CRAM”) for a field programmable gate array (“FPGA”) integrated circuit (“IC”) device is given increased resistance to single event upset (“SEU”). A...
7465970 Common pass gate layout of a D flip flop  
A semiconductor layout includes a p substrate, a first semiconductor cell formed over the p substrate, and a second semiconductor cell formed over the p substrate adjacent to the first...
7456508 Hosting structure of nanometric elements and corresponding manufacturing method  
A hosting structure of nanometric components is described comprising a substrate, a first multi-spacer level comprising a first plurality of spacers including first conductive spacers parallel to...
7456446 Semiconductor device  
A semiconductor device of the generation with the minimum processing dimensions of 90 nm, or later, wherein variation of processing dimensions of gate electrodes in a logic block and a power source...
7446418 Semiconductor device for preventing defective filling of interconnection and cracking of insulating film  
The semiconductor device has insulating films 40, 42 formed over a substrate 10 ; an interconnection 58 buried in at least a surface side of the insulating films 40, 42 ; insulating films ...
7439894 Electronic apparatus for current source array and layout method thereof  
An electronic apparatus for current source array and the layout method thereof are provided. The current source array includes a low bit group and a plurality of high bit groups. The low bit group...
7436007 Master slice type semiconductor integrated circuit device  
A plurality of terminals is formed in a basic cell. One terminal has first to fifth patterns. The first and second patterns are arranged to be spaced from each other. The third and fourth patterns...
7422945 Cell based integrated circuit and unit cell architecture therefor  
In a unit cell, a first conductive type active region and a second conductive type active region are provided. Those two active regions extend in a first direction. Each of the active regions have...
7423324 Double-gate MOS transistor, double-gate CMOS transistor, and method for manufacturing the same  
In a double-gate MOS transistor, a substrate, an insulating layer, and a semiconductor layer are formed or laminated in that order, an opening extending to the insulating layer is formed in the...
7402847 Programmable logic circuit and method of using same  
A programmable logic circuit, including programmable memory element, suitable for microprocessor applications, and a method of using the circuit are disclosed. The programmable circuit includes at...
7402846 Electrostatic discharge (ESD) protection structure and a circuit using the same  
An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure includes an active device. The active device includes a plurality of drains. Each of the drains has...
7399675 Electronic device including an array and process for forming the same  
An electronic device can include an NVM array, wherein portions of word lines are formed within trenches. Insulating features are formed over heavily doped regions within the substrate. In one...
7394115 Semiconductor integrated circuit device having clock signal transmission line and wiring method thereof  
A clock signal transmission line in the semiconductor integrated circuit device includes a plurality of straight portions arranged side by side in a predetermined direction and a plurality of bent...
7385249 Transistor structure and integrated circuit  
A process for forming a conductive gate structure for a sub-0.25 MOSFET technology, has been developed. The process features a conductive gate structure defined from a composite polysilicon or...
7385233 Gate array integrated circuit including a unit cell basic layer having gate terminal regions allowing two contact pads to be disposed laterally  
A gate array integrated circuit forming part of a semiconductor integrated circuit includes a basic layer of a unit cell in which a PMOS and an NMOS transistor are connected with a poly-silicon...
7382155 Enhanced field programmable gate array  
An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same...
7379319 Semiconductor integrated circuit device  
A semiconductor integrated circuit device includes a semiconductor substrate and a plurality of cell transistors provided on a surface of the semiconductor substrate. A local bit line is provided...
7368787 Fin field effect transistors (FinFETs) and methods for making the same  
In a first aspect, a first method is provided for semiconductor device manufacturing. The first method includes the steps of (1) forming a first side of a fin of a fin field effect transistor...
7368767 Semiconductor integrated circuit device formed by automatic layout wiring by use of standard cells and design method of fixing its well potential  
A standard cell is read from a library and automatic layout wiring is performed, thereby configuring a circuit. Next, each cell column in the configured circuit is searched for an empty region. In...
7358547 Selective deposition to improve selectivity and structures formed thereby  
Methods and associated apparatus of forming a microelectronic structure are described. Those methods comprise providing a substrate comprising a region of higher active area density comprising...
Matches 1 - 50 out of 342 1 2 3 4 5 6 7 >