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8659055 Semiconductor device, field-effect transistor, and electronic device  
Provided is a semiconductor device capable of suppressing an occurrence of a punch-through phenomenon. A semiconductor device includes a substrate 1, a first n-type semiconductor layer 2, a p-type...
8659054 Method and structure for pFET junction profile with SiGe channel  
A semiconductor structure including a p-channel field effect transistor (pFET) device located on a surface of a silicon germanium (SiGe) channel is provided in which the junction profile of the...
8659020 Epitaxial silicon wafer and method for manufacturing same  
It is an object to provide an epitaxial silicon wafer that is provided with an excellent gettering ability in which a polysilicon layer is formed on the rear face side of a silicon crystal...
8653604 Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer  
Multiple transistor types are formed in a common epitaxial layer by differential out-diffusion from a doped underlayer. Differential out-diffusion affects the thickness of a FET channel, the...
8653558 Semiconductor device and method of making  
In some embodiments, a metal insulator semiconductor heterostructure field effect transistor (MISHFET) is disclosed that has a source, a drain, an insulation layer, a gate dielectric, and a gate....
8653559 AlGaN/GaN hybrid MOS-HFET  
A field effect transistor (FET) includes source and drain electrodes, a channel layer, a barrier layer over the channel layer, a passivation layer covering the barrier layer for passivating the...
8653561 III-nitride semiconductor electronic device, and method of fabricating III-nitride semiconductor electronic device  
A III-nitride semiconductor electronic device comprises a semiconductor laminate provided on a primary surface of a substrate, a first electrode in contact with the semiconductor laminate, and a...
8653560 Semiconductor device and fabrication method thereof  
According to one embodiment, a fabrication method of a semiconductor device comprising forming a dummy gate with a gate length direction set to a [111] direction perpendicular to a [110] direction...
8647935 Buried oxidation for enhanced mobility  
A method patterns at least one pair of openings through a protective layer and into a substrate. The openings are positioned on opposite sides of a channel region of the substrate. The method...
8648388 High performance multi-finger strained silicon germanium channel PFET and method of fabrication  
A field effect transistor and method of fabrication are provided. The field effect transistor comprises a plurality of elongated uniaxially-strained SiGe regions disposed on a silicon substrate,...
8643061 Structure of high-K metal gate semiconductor transistor  
A semiconductor structure is provided. The structure includes an n-type field-effect-transistor (NFET) being formed directly on top of a strained silicon layer, and a p-type...
8643062 III-N device structures and methods  
A III-N device is described with a III-N layer, an electrode thereon, a passivation layer adjacent the III-N layer and electrode, a thick insulating layer adjacent the passivation layer and...
8637373 Transistors and methods of manufacturing the same  
In a method of manufacturing a transistor, a gate structure is formed on a substrate including silicon. An upper portion of the substrate adjacent to the gate structure is etched to form a first...
8637358 Field-effect-transistor with self-aligned diffusion contact  
Embodiments of the present invention provide a method of forming fin-type transistors having replace-gate electrodes with self-aligned diffusion contacts. The method includes forming one or more...
8637850 Transport conduits for contacts to graphene  
An apparatus comprises at least one transistor. The at least one transistor comprises a substrate, a graphene layer formed on the substrate, and first and second source/drain regions spaced apart...
8633518 Gallium nitride power devices  
Enhancement mode III-nitride devices are described. The 2DEG is depleted in the gate region so that the device is unable to conduct current when no bias is applied at the gate. Both gallium face...
8633515 Transistors with immersed contacts  
Embodiments of a semiconductor structure include a first current electrode region, a second current electrode region, and a channel region. The channel region is located between the first current...
8633470 Techniques and configurations to impart strain to integrated circuit devices  
Embodiments of the present disclosure describe techniques and configurations to impart strain to integrated circuit devices such as horizontal field effect transistors. An integrated circuit...
8633106 Heterojunction bipolar transistors and methods of manufacture  
Semiconductor structures and methods of manufacture semiconductors are provided which relate to heterojunction bipolar transistors. The method includes forming two devices connected by metal wires...
8633094 GaN high voltage HFET with passivation plus gate dielectric multilayer structure  
A method of fabricating a multi-layer structure for a power transistor device includes performing, within a reaction chamber, a nitrogen plasma strike, resulting in the formation of a nitride...
8633516 Source/drain stack stressor for semiconductor device  
The present disclosure provides a semiconductor device. The device includes a substrate, a fin structure formed by a first semiconductor material, a gate region on a portion of the fin, a source...
8633514 Group III nitride semiconductor wafer and group III nitride semiconductor device  
A group III nitride semiconductor device and a group III nitride semiconductor wafer are provided. The group III nitride semiconductor device has a channel layer comprising group III nitride-based...
8633471 Apparatus and methods for forming a modulation doped non-planar transistor  
Embodiments of an apparatus and methods for providing three-dimensional complementary metal oxide semiconductor devices comprising modulation doped transistors are generally described herein....
8629016 Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer  
Multiple transistor types are formed in a common epitaxial layer by differential out-diffusion from a doped underlayer. Differential out-diffusion affects the thickness of a FET channel, the...
8629479 Semiconductor device  
A semiconductor device includes a first GaN layer provided on a SiC substrate, a second GaN layer provided on the first GaN layer, and an electron supply layer that is provided on the second GaN...
8629478 Fin structure for high mobility multiple-gate transistor  
A vertical fin structure for a semiconductor transistor includes a semiconductor substrate, a fin layer on top of the substrate, a capping layer overlaying the fin layer, wherein the substrate...
8629480 Hetero-junction tunneling transistor  
A hetero-junction tunneling transistor having a first layer of p++ silicon germanium which forms a source for the transistor at one end. A second layer of n+ silicon material is deposited so that...
8629454 Semiconductor device  
A semiconductor device includes: a nitride semiconductor layer; a source electrode, a gate electrode and a drain electrode; an insulating layer covering at least the gate electrode and a part of...
8624303 Field effect transistor  
A lateral field-effect transistor capable of improving switching speed and reducing operationally defective products is provided. A gate wiring has a base, a plurality of fingers protruding from...
8624261 Nitride semiconductor device  
According to one embodiment, a nitride semiconductor device includes a first, a second, a third and a fourth transistor of n-type channel and a resistor. The first transistor has a first gate, a...
8624304 Printed material constrained by well structures and devices including same  
A first patterned contact layer, for example a gate electrode, is formed over an insulative substrate. Insulating and functional layers are formed at least over the first patterned contact layer....
8618577 Compound semiconductor device and manufacturing method thereof  
An n-type GaN layer (3), a GaN layer (7) formed over the n-type GaN layer (3), an n-type AlGaN layer (9) formed over the GaN layer (7), a gate electrode (15) and a source electrode (13) formed...
8618578 Field effect transistor  
A field effect transistor includes a nitride-based semiconductor multi-layer structure, a source electrode (108), a drain electrode (109), a protective film (110), and a gate electrode (112) that...
8618534 Field-effect transistor with a dielectric layer having therein denatured albumen  
A field-effect transistor includes a gate electrode, a source electrode, a drain electrode, a semiconductor active layer, and a dielectric layer. The semiconductor active layer is connected to the...
8614461 Compound semiconductor device  
The compound semiconductor device comprises an i-GaN buffer layer 12 formed on an SiC substrate 10; an n-AlGaN electron supplying layer 16 formed on the i-GaN buffer layer 12; an n-GaN cap layer...
8614460 Semiconductor device and fabrication method of the semiconductor device  
A semiconductor device and a fabrication method of the semiconductor device, the semiconductor device including: a substrate; a nitride based compound semiconductor layer placed on the substrate...
8610173 Enhancement/depletion PHEMT device  
An embodiment of the present invention concerns a layered epitaxial structure for enhancement/depletion PHEMT devices, an enhancement/depletion PHEMT device and a method for manufacturing an...
8610130 Monolithic high voltage switching devices  
Metal oxide semiconductor (MOS) power devices are provided including a MOS channel including a semiconductor material having high electron mobility on a silicon carbide (SiC) layer. Related...
8610172 FETs with hybrid channel materials  
Techniques for employing different channel materials within the same CMOS circuit are provided. In one aspect, a method of fabricating a CMOS circuit includes the following steps. A wafer is...
8604519 Self-aligned III-V field effect transistor (FET) and integrated circuit (IC) chip  
Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations are defined on a layered semiconductor wafer. The layered...
8604517 Non-volatile semiconductor memory device for suppressing deterioration in junction breakdown voltage and surface breakdown voltage of transistor  
According to one embodiment, a non-volatile semiconductor memory device includes a plurality of memory cells and a transistor. The transistor includes a gate insulating film, a gate electrode on...
8604518 Split-channel transistor and methods for forming the same  
A Fin Field-Effect Transistor (FinFET) includes a fin, which includes a channel splitter having a first bandgap, and a channel including a first portion and a second portion on opposite sidewalls...
8603880 Semiconductor device including gate electrode provided over active region in P-type nitride semiconductor layer and method of manufacturing the same, and power supply apparatus  
A semiconductor device includes a nitride semiconductor stacked structure including a carrier transit layer and a carrier supply layer; a p-type nitride semiconductor layer provided over the...
8598626 Epitaxial substrate for semiconductor device, schottky junction structure, and leakage current suppression method for schottky junction structure  
Provided is an epitaxial substrate for semiconductor device that is capable of achieving a semiconductor device having high reliability in reverse characteristics of schottky junction. An...
8598006 Strain preserving ion implantation methods  
An embedded epitaxial semiconductor portion having a different composition than matrix of the semiconductor substrate is formed with a lattice mismatch and epitaxial alignment with the matrix of...
8598628 Semiconductor device  
A normally off semiconductor device with a reduced off-state leakage current, which is applicable to a power switching element, includes: a substrate; an undoped GaN layer formed above the...
8598627 P-type field-effect transistor and method of production  
An n-layer is arranged above a substrate, which can be GaAs, and a p-layer (4) is arranged on the n-layer. The p-layer is separated by a gate electrode into two separate portions forming source...
8592289 Epitaxial wafer, method for manufacturing gallium nitride semiconductor device, gallium nitride semiconductor device and gallium oxide wafer  
A gallium nitride based semiconductor device is provided which includes a gallium nitride based semiconductor film with a flat c-plane surface provided on a gallium oxide wafer. A light emitting...
8592865 Overvoltage tolerant HFETs  
Design constraints for a self protecting GaN HFET and in general any group III V HFET are described. The design constraints depend on the separation between the gate and the drain and the...
8592862 Gallium nitride semiconductor structures with compositionally-graded transition layer  
The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials...