|
Match
|
Document |
Document Title |
|
|
8174046 |
Reducing effects of parasitic transistors in thyristor-based memory using local thinning or implanting
Method and apparatus for an integrated circuit having memory including thyristor-based memory cells is described. A pair of the thyristor-based memory cells are commonly coupled via a bitline...
|
|
|
8148748 |
Adjustable field effect rectifier
An Adjustable Field Effect Rectifier uses aspects of MOSFET structure together with an adjustment pocket or region to result in a device that functions reliably and efficiently at high voltages...
|
|
|
8084815 |
Superjunction semiconductor device
A superjunction semiconductor device includes an edge p pillar, an active region, and a termination region. The edge p pillar has a rectangular ring shape with rounded corners surrounding the...
|
|
|
8008121 |
Semiconductor package and method of mounting semiconductor die to opposite sides of TSV substrate
A semiconductor package has a first conductive via formed through a substrate. The substrate with first conductive via is mounted to a first carrier. A first semiconductor die is mounted to a first...
|
|
|
8008734 |
Power semiconductor device
A power semiconductor device is provided having a field plate that employs a thick metal film in an edge termination structure and which permits edge termination structure width reduction even with...
|
|
|
8008733 |
Semiconductor device having a power cutoff transistor
Disclosed herein is a semiconductor device having a power cutoff transistor including a semiconductor substrate of a first conductivity type; and first and second wells of the first conductivity...
|
|
|
7999284 |
Semiconductor device and optical device module having the same
A solid-state imaging device 1 is arranged so that a hollow section 9 is formed between a solid-state imaging element 2 and a covering section 4 and an air path 7 is formed in an adhesive section 5...
|
|
|
7968976 |
Guard ring extension to prevent reliability failures
An embodiment of the present invention is a technique to prevent reliability failures in semiconductor devices. A trench is patterned in a polyimide layer over a guard ring having a top metal...
|
|
|
7893459 |
Seal ring structures with reduced moisture-induced reliability degradation
A semiconductor chip includes a seal ring adjacent to edges of the semiconductor chip; an opening extending from a top surface to a bottom surface of the seal ring, wherein the opening has a first...
|
|
|
7834351 |
Semiconductor device
A semiconductor device is disclosed. The device includes a substrate and a first wiring layer overlying the substrate. The first wiring layer comprises a first wiring area surrounded by a first...
|
|
|
7777248 |
Semiconductor device for latch-up prevention
A semiconductor device is provided for preventing Latch-up in Silicon Controlled Rectifiers (SCRs) when these SCRs become activated. Embodiments of the invention use a natively doped region having...
|
|
|
7763916 |
Substrate table
A substrate table used for manufacturing a chip is provided. The substrate table includes a substrate stage, a substrate placement surface formed on the substrate stage, and on which a substrate is...
|
|
|
7759173 |
Methods for charge dissipation in integrated circuits
Methods and structures and methods of designing structures for charge dissipation in an integrated circuit on an SOI substrate. A first structure includes a charge dissipation ring around a...
|
|
|
7759734 |
Semiconductor device
A semiconductor device including a plurality of doped regions, a metal layer and a polysilicon layer is provided. The doped regions are disposed in a substrate. The metal layer includes a plurality...
|
|
|
7705462 |
Semiconductor device and a method of manufacturing the same
A semiconductor IC device which includes a circuit region and a peripheral region on a main surface of a semiconductor substrate, a first insulating film formed over the main surface, external...
|
|
|
7667242 |
Systems and methods for maximizing breakdown voltage in semiconductor devices
Systems and methods for maximizing the breakdown voltage of a semiconductor device are described. In a multiple floating guard ring design, the spacing between two consecutive sets of floating...
|
|
|
7663159 |
Seal ring corner design
Techniques for an integrated circuit device are provided. The integrated circuit device includes a substrate, an active circuit area, and a dielectric layer. A seal ring surrounds the active...
|
|
|
7649213 |
Semiconductor device
A semiconductor device includes an SiC substrate, a normal direction of the substrate surface being off from a <0001> or <000-1> direction in an off direction, an SiC layer formed on the SiC...
|
|
|
7612371 |
Structure to monitor arcing in the processing steps of metal layer build on silicon-on-insulator semiconductors
The present invention addresses detection of charge-induced defects through test structures that can be easily incorporated on a wafer to detect charge-induced damage in the back-end-of-line...
|
|
|
7582918 |
Semiconductor device with enhanced breakdown voltage
In a peripheral portion of an IGBT chip, an intermediate potential electrode (20) is provided between a field plate (14) and a field plate (15) on a field oxide film (13), to surround an IGBT cell....
|
|
|
7576369 |
Deep diffused thin photodiodes
This invention comprises photodiodes, optionally organized in the form of an array, including p+ deep diffused regions or p+ and n+ deep diffused regions. More specifically, the invention permits...
|
|
|
7566914 |
Devices with adjustable dual-polarity trigger- and holding-voltage/current for high level of electrostatic discharge protection in sub-micron mixed signal CMOS/BiCMOS integrated circuits
Symmetrical/asymmetrical bidirectional S-shaped I-V characteristics with trigger voltages ranging from 10 V to over 40 V and relatively high holding current are obtained for advanced sub-micron...
|
|
|
7566915 |
Guard ring extension to prevent reliability failures
An embodiment of the present invention is a technique to prevent reliability failures in semiconductor devices. A trench is patterned in a polyimide layer over a guard ring having a top metal...
|
|
|
7554131 |
Chip embedded package structure and fabrication method thereof
A chip embedded package structure and a fabrication method thereof are proposed. An adhesive layer is formed on a bottom surface of a carrier board having at least one cavity to seal one end of the...
|
|
|
7538346 |
Semiconductor device
A semiconductor device is disclosed. The device includes a substrate and a first wiring layer overlying the substrate. The first wiring layer comprises a first wiring area surrounded by a first...
|
|
|
7525178 |
Semiconductor device with capacitively coupled field plate
A termination region of a semiconductor die is provided, which includes one or more field rings arranged in the termination region, one or more metal field plates, and an insulation layer disposed...
|
|
|
7517762 |
Semiconductor device capable of preventing moisture-absorption of fuse area thereof and method for manufacturing the fuse area
A fuse area of a semiconductor device capable of preventing moisture-absorption and a method for manufacturing the fuse area are provided. When forming a guard ring for preventing permeation of...
|
|
|
7408206 |
Method and structure for charge dissipation in integrated circuits
Methods and structures and methods of designing structures for charge dissipation in an integrated circuit on an SOI substrate. A first structure includes a charge dissipation ring around a...
|
|
|
7409660 |
Method and end cell library for avoiding substrate noise in an integrated circuit
A method of avoiding substrate noise in an integrated circuit includes steps of receiving as input an integrated circuit design that includes at least a portion of a block for placement and routing...
|
|
|
7391093 |
Semiconductor device with a guard-ring structure and a field plate formed of polycrystalline silicon film embedded in an insulating film
A semiconductor device has a semiconductor device chip with upper and lower terminal electrodes, and upper and lower frames bonded to the upper and lower terminal electrodes, respectively, with...
|
|
|
7329894 |
Semiconductor laser device and semiconductor optical modulator
Since the semiconductor devices including a stacked structure of group-III-V alloy semiconductor layers different in the kind of group-V constituent atom form the so-called band line-up of type II,...
|
|
|
7326974 |
Sensor for measuring a gas concentration or ion concentration
A field-effect transistor used as a sensor for measuring a gas or ion concentration utilizes a surface structure such as rings along with surface profiling, for example elevations of the rings and...
|
|
|
7309628 |
Method of forming a semiconductor device
A semiconductor device is formed as part of an integrated circuit. The semiconductor device, which is formed in an active semiconductor layer, is surrounded by a guardian that provides a diffusion...
|
|
|
7288799 |
Semiconductor device and fabrication method thereof
A semiconductor device includes a semiconductor substrate, a circuit part formed on and above the semiconductor substrate, a passivation film covering the circuit part, an electrode pad provided...
|
|
|
7276743 |
Retaining ring with conductive portion
A retaining ring for use with electrochemical mechanical processing is described. The retaining ring has a generally annular body formed with a conductive portion and a non-conductive portion. The...
|
|
|
7268421 |
Semiconductor chip assembly with welded metal pillar that includes enlarged ball bond
A semiconductor chip assembly includes a semiconductor chip that includes a conductive pad, a conductive trace that includes a routing line and a metal pillar, a connection joint that electrically...
|
|
|
7169699 |
Semiconductor device having a guard ring
A semiconductor device has a guard ring in a multilayer interconnection structure, wherein the guard ring includes a conductive wall extending zigzag in a plane parallel with a principal surface of...
|
|
|
7151302 |
Method and apparatus for maintaining topographical uniformity of a semiconductor memory array
A semiconductor device includes a memory array having a plurality of non-volatile memory cells. Each non-volatile memory cell of the plurality of non-volatile memory cells has a gate stack. The...
|
|
|
7135718 |
Diode device and transistor device
A semiconductor device having improved breakdown voltage is provided. A diode device of the present invention includes relay diffusion layers provided between guard ring portions. Therefore, a...
|
|
|
7132696 |
Intermeshed guard bands for multiple voltage supply structures on an integrated circuit, and methods of making same
The present invention is generally directed to intermeshed guard bands for multiple voltage supply regions or structures on an integrated circuit, and methods of making same. In one illustrative...
|
|
|
7132316 |
After deposition method of thinning film to reduce pinhole defects
A method of forming a thin film is provided in which a film having a first thickness is deposited over a substrate, wherein the first thickness is greater than a thickness at which the initially...
|
|
|
7129544 |
Vertical compound semiconductor field effect transistor structure
In one embodiment, a compound semiconductor vertical FET device (11) includes a first trench (29) formed in a body of semiconductor material (13), and a second trench (34) formed within the first...
|
|
|
7053453 |
Substrate contact and method of forming the same
A substrate contact and semiconductor chip, and methods of forming the same. The substrate contact is employable with a semiconductor chip formed from a semiconductor substrate and includes a seal...
|
|
|
7053356 |
Photodetection cell and laser pulse detector having a cascoded inverting amplifier looped back through a slow follower type feedback
Photodetection cell and laser pulse detector furnished with such a cell, as well as laser pulse detection device comprising a matrix of such detectors. The photodetection cell (1) is embodied in...
|
|
|
7009222 |
Protective metal structure and method to protect low-K dielectric layer during fuse blow process
A method to protect a low-K IMD layer underlying a fuse link during a fuse blowing process including a guarded fuse and method for forming the same including forming a fuse portion comprising two...
|
|
|
7002187 |
Integrated schottky diode using buried power buss structure and method for making same
An integrated Schottky diode and method of manufacture of such a diode is disclosed. In a first aspect, a Schottky diode comprises a semiconductor substrate. The semiconductor substrate includes an...
|
|
|
6989552 |
Method for making an integrated circuit device with dielectrically isolated tubs and related circuit
A method for making an integrated circuit includes forming spaced-apart trenches on a surface of a single crystal silicon substrate, lining the trenches with a silicon oxide layer, forming a first...
|
|
|
6965130 |
Alternating implant ring terminations
A semiconductor device including a semiconductive body having formed therein an active region and a termination feature which includes spaced field rings disposed around the active region and...
|
|
|
6940131 |
MOS ESD CDM clamp with integral substrate injection guardring and method for fabrication
The present invention includes a MOS device (100) that has a P-type substrate (102) and an N-type drain region (104) formed within the substrate (102). An annular N-type source region (106)...
|
|
|
6921930 |
Pulse-controlled bistable bidirectional electronic switch
The invention concerns a bidirectional electronic switch of the pulse-controlled bistable type comprising a monolithic semiconductor circuit including a vertical bidirectional switch structure (TR;...
|