Matches 351 - 400 out of 16945 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >
Match Document Document Title
7332735 Phase change memory cell and method of formation  
A phase change memory element and methods for forming the same are provided. The memory element includes a first electrode and a chalcogenide comprising phase change material layer over the first...
7332703 Imaging structure including a pixel with multiple signal readout circuits and methods of operation for imaging structure  
A pixel cell allows both correlated double sampling (CDS) and automatic light control (ALC) operations through a non-destructive, parallel readout. An image sensor may include an array of pixel...
7332442 Systems and methods for forming metal oxide layers  
A method of forming (and apparatus for forming) a metal oxide layer, preferably a dielectric layer, on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor...
7332419 Structure and method of fabricating a transistor having a trench gate  
An integrated circuit transistor is fabricated with a trench gate having nonconductive sidewalls. The transistor is surrounded by an isolation trench filled with a nonconductive material. The...
7332418 High-density single transistor vertical memory gain cell  
A memory cell which is formed on a substrate of a first conductivity type. A pillar of the first conductivity type extends vertically upward from the substrate. A source region of a second...
7332413 Semiconductor wafers including one or more reinforcement structures and methods of forming the same  
Methods of forming semiconductor devices include thinning a region of a semiconductor wafer and forming at least one semiconductor die laterally within a thinned region of the wafer. One or more...
7332408 Isolation trenches for memory devices  
Methods and apparatus are provided. A first dielectric plug is formed in a portion of a trench that extends into a substrate of a memory device so that an upper surface of the first dielectric plug...
7332401 Method of fabricating an electrode structure for use in an integrated circuit  
An electrode structure includes a first layer of conductive material and a dielectric layer formed on a surface of the first layer. An opening is formed in the dielectric layer to expose a portion...
7332389 Selective polysilicon stud growth  
A memory cell having a bit line contact is provided. The memory cell may be a 6F 2 memory cell. The bit line contact may have a contact hole bounded by insulating sidewalls, and the contact hole...
7332388 Method to simultaneously form both fully silicided and partially silicided dual work function transistor gates during the manufacture of a semiconductor device, semiconductor devices, and systems including same  
A method for forming transistor gates having two different work functions comprises forming a first polysilicon layer which may be doped with n-type dopants. The first polysilicon layer comprises...
7332376 Method of encapsulating packaged microelectronic devices with a barrier  
Methods and apparatuses for encapsulating a microelectronic die or other components in the fabrication of packaged microelectronic devices. In one aspect of the invention, a packaged...
7332372 Methods for forming assemblies and packages that include stacked semiconductor devices separated a distance defined by adhesive material interposed therebetween  
A method for assembling semiconductor devices includes providing a first semiconductor device, applying a volume of adhesive material to at least a surface of the first semiconductor device, and...
7332032 Precursor mixtures for use in preparing layers on substrates  
Methods of forming a layer on a substrate using complexes of Formula I. The complexes and methods are particularly suitable for the preparation of semiconductor structures. The complexes are of the...
RE40061 Multi-chip stacked devices  
A multiple stacked die device is disclosed that contains up to four dies and does not exceed the height of current single die packages. Close-tolerance stacking is made possible by a...
7330992 System and method for read synchronization of memory modules  
A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to...
7330929 CAM modified to be used for statistic calculation in network switches and routers  
A content addressable memory (CAM) device includes a plurality of entries each having an associated counter. When a CAM entry matches a search word stored in the comparand register of the CAM...
7330869 Hybrid arithmetic logic unit  
Methods and apparatus for improving the efficiency of an arithmetic logic unit (ALU) are provided. The ALU of the invention combines the operation of a single-cycle ALU with the processing speed of...
7330393 Memory array decoder  
An apparatus and method for selecting a storage location in a memory device including receiving at least one of a pre-decoded location address signal, a match signal, and a redundant location...
7330390 Noise resistant small signal sensing circuit for a memory device  
Apparatus and method for data sensing circuitry that uses averaging to sense small differences in signal levels representing data states. The apparatus periodically switches the coupling of input...
7330382 Programmable DQS preamble  
A method and apparatus for programming a data strobe (DQS) preamble in a memory by loading a defined set of bits into one or more registers of the memory, where one or more bits are formatted...
7330367 Stacked 1T-nMTJ MRAM structure  
This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and...
7330211 Camera module with focus adjustment structure and systems and methods of making the same  
Camera modules with focus adjustment structures and systems and methods of making the same are described. In one aspect, a sensor housing having an image sensor, a lens holder comprising a lens,...
7330146 Minimized SAR-type column-wide ADC for image sensors  
An improved analog-to-digital converter wherein a minimal amount of circuitry is provided for conversion of an analog signal to a series of digital bits. A comparator is provided for generating...
7330036 Engagement Probes  
An engagement probe for engaging electrically conductive test pads on a semiconductor substrate having integrated circuitry for operability testing thereof includes an outer surface comprising a...
7329949 Packaged microelectronic devices and methods for packaging microelectronic devices  
Packaged microelectronic devices and methods for packaging microelectronic devices are disclosed herein. In one embodiment, a method of packaging a microelectronic device including a...
7329945 Flip-chip adaptor package for bare die  
A board for connecting a bare semiconductor die with a bond pad arrangement which does not conform to a master printed circuit board with a specific or standardized pin out, connector pad, or lead...
7329943 Microelectronic devices and methods for forming interconnects in microelectronic devices  
Microelectronic devices, methods for packaging microelectronic devices, and methods for forming interconnects in microelectronic devices are disclosed herein. In one embodiment, a method comprises...
7329924 Integrated circuits and methods of forming a field effect transistor  
Integrated circuits and methods of forming field effect transistors are disclosed. In one aspect, an integrated circuit includes a semiconductor substrate comprising bulk semiconductive material....
7329920 Trench corner effect bidirectional flash memory cell  
A non-volatile memory cell structure that is capable of holding two data bits. The structure includes a trench in a substrate with two sides of the trench being lined with a trapping material. The...
7329917 Permeable capacitor electrode  
The present teachings describe a container capacitor that utilizes an etchant permeable lower electrode for the formation of single or double-sided capacitors without excessive etching back of the...
7329910 Semiconductor substrates and field effect transistor constructions  
The invention includes methods of forming field effect transistor gates. In one implementation, a series of layers is formed proximate a semiconductive material channel region. The layers comprise...
7329899 Wafer-level redistribution circuit  
A semiconductor component configured for wafer-level testing includes a semiconductor die having at least one die contact electrically exposed for coupling with a redistribution circuit that...
7329861 Integrally packaged imaging module  
An integrally packaged imaging module includes an integrated circuit (IC), including an image sensing device formed on a semiconductor substrate, and wafer level packaging enclosing the IC. The...
7329856 Image sensor having integrated infrared-filtering optical device and related method  
An image sensing device is disclosed having a die formed with an array of photosensing sites and a structure of optical material having infrared absorbing characteristics formed over the...
7329618 Ion implanting methods  
An ion implanting method includes forming a pair of spaced and adjacent features projecting outwardly from a substrate. At least outermost portions of the pair of spaced features are laterally...
7329615 Atomic layer deposition method of forming an oxide comprising layer on a substrate  
This invention includes atomic layer deposition methods of depositing oxide comprising layers on substrates. In one implementation, a substrate is positioned within a deposition chamber. A first...
7329607 Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby  
A conductive connection forming method includes forming a first layer comprising a first metal on a substrate and forming a second layer comprising a second metal different from the first metal on...
7329576 Double-sided container capacitors using a sacrificial layer  
Double-sided container capacitors are formed using sacrificial layers. A sacrificial layer is formed within a recess in a structural layer. A lower electrode is formed within the recess. The...
7329573 Methods of forming capacitors  
A method of forming a capacitor includes forming a first capacitor electrode over a semiconductor substrate. A capacitor dielectric region is formed onto the first capacitor electrode. The...
7329558 Differential negative resistance memory  
The invention relates to a DNR (differential negative resistance) exhibiting device that can be programmed to store information as readable current amplitudes and to methods of making such a...
7329552 Field effect transistor fabrication methods, field emission device fabrication methods, and field emission device operational methods  
The present invention includes field effect transistors, field emission apparatuses, thin film transistors, and methods of forming field effect transistors. According to one embodiment, a field...
7329292 Process byproduct trap and system including same  
A trap device including at least one substance delivery element for introducing a substance therein is disclosed. The delivered substance may influence the nature of deposits that have formed...
7329168 Extended Kalman filter incorporating offline metrology  
An algorithm uses offline metrology to control a process by passing information from an outer control loop to an inner control loop, extended Kalman filter estimator. The inner control loop...
7328517 Method and apparatus for measurement of thickness and warpage of substrates  
An apparatus comprises one or more pairs of mutually coaxial and opposing linear measuring devices including movable, biased fingers for simultaneously determining the thickness and warpage of a...
7328381 Testing system and method for memory modules having a memory hub architecture  
A testing method and system is used to test memory modules each of which has a memory hub coupled to a plurality of memory devices. The testing system and method includes a test interface circuit...
7328379 Look-up table for use with redundant memory  
A redundancy scheme for a memory is disclosed that is programmable both before and after the memory device is packaged and/or installed in a system. This is preferably accomplished by using...
7327629 Circuit and method for reading an antifuse  
An antifuse circuit and antifuse reading method for determining whether an antifuse is programmed or un-programmed. An antifuse circuit includes a sensing circuit having a sense node coupled to the...
7327628 Circuit and method for reading an antifuse  
An antifuse circuit and antifuse reading method for determining whether an antifuse is programmed or un-programmed. An antifuse circuit includes a sensing circuit having a sense node coupled to the...
7327618 Semiconductor memory with wordline timing  
A semiconductor memory with wordline timing, which links activating a wordline to an isolation signal. The isolation signal is applied to a memory section adjacent the memory section containing the...
7327592 Self-identifying stacked die semiconductor components  
A semiconductor die having a functional circuit (e.g., a memory array) and a decode circuit suitable for use in a stacked die semiconductor component (e.g., a random access memory component) is...
Matches 351 - 400 out of 16945 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >