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7575953 |
Stacked die with a recess in a die BGA package
Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies for increasing semiconductor device density are provided.
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7574634 |
Real time testing using on die termination (ODT) circuit
A system and method to operate an electronic device, such as a memory chip, in a test mode using the device's built-in ODT (on die termination) circuit is disclosed. One or more test mode related...
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7573752 |
NAND flash memory cell programming
A flash memory device, such as a NAND flash, is described having an array of floating gate transistor memory cells arranged in a first and second addressable blocks. A voltage source to supply...
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7573738 |
Mode selection in a flash memory device
A single flash memory device has selectable read modes for either a segment mode or a page mode. The desired mode is selected by writing a control word to a mode control register. Selecting the...
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7573733 |
Self-identifying stacked die semiconductor components
A semiconductor die having a functional circuit (e.g., a memory array) and a decode circuit suitable for use in a stacked die semiconductor component (e.g., a random access memory component) is...
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7573288 |
Dynamically adjusting operation of a circuit within a semiconductor device
Systems and methods for dynamically adjusting operation of a circuit within a semiconductor device are described herein. At least some illustrative embodiments include a system that includes a...
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7573276 |
Probe card layout
Multi-touchdown, parallel test probe cards having probe elements arranged to provide greater than 99% efficiency during testing of a substrate having a plurality of die thereon, and methods of use.
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7573136 |
Semiconductor device assemblies and packages including multiple semiconductor device components
A multidie semiconductor device assembly or package includes an interposer comprising a substrate with at least one receptacle therethrough. A plurality of semiconductor device components (e.g.,...
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7573125 |
Methods for reducing stress in microelectronic devices and microelectronic devices formed using such methods
Methods for reducing stress in microelectronic devices and microelectronic devices formed using such methods are disclosed herein. One such device can include a first support member, a second...
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7573121 |
Method for enhancing electrode surface area in DRAM cell capacitors
Methods for forming the lower electrode of a capacitor in a semiconductor circuit, and the capacitors formed by such methods are provided. The lower electrode is fabricated by forming a texturizing...
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7573116 |
Etch aided by electrically shorting upper and lower sidewall portions during the formation of a semiconductor device
A method used to fabricate a semiconductor device comprises etching a dielectric layer, resulting in an undesirable charge buildup along a sidewall formed in the dielectric layer during the etch....
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7573108 |
Non-planar transistor and techniques for fabricating the same
A non-planar transistor and methods for fabricating the same. In certain embodiments, the transistor includes an active gate and a passive gate. The active gate may be switchably coupled to a first...
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7573088 |
DRAM array and electronic system
The invention includes a semiconductor construction including rows of contact plugs, and rows of parallel bottom plates. The plug pitch is approximately double the plate pitch. The invention...
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7573087 |
Interconnect line selectively isolated from an underlying contact plug
A means for selectively electrically connecting an electrical interconnect line, such as a bit line of a memory cell, with an associated contact stud and electrically isolating the interconnect...
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7573021 |
Method and apparatus for multiple scan rate swept wavelength laser-based optical sensor interrogation system with optical path length measurement capability
The invention relates to optical sensor measurement methods that use a swept wavelength optical source to determine wavelength shift as well as to optical sensor systems that embody and employ...
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7573006 |
Apparatus relating to the reconstruction of semiconductor wafers for wafer-level processing
Apparatus, systems and methods relating to the reconstruction of semiconductor wafers for wafer-level processing are disclosed. Selected semiconductor dice having alignment cavities formed in a...
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7572731 |
Unsymmetrical ligand sources, reduced symmetry metal-containing compounds, and systems and methods including same
The present invention provides metal-containing compounds that include at least one β-diketiminate ligand, and methods of making and using the same. In some embodiments, the metal-containing...
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7572710 |
Methods of forming conductive contacts to source/drain regions and methods of forming local interconnects
The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local interconnects. In one implementation, a method of...
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7572695 |
Hafnium titanium oxide films
Embodiments of a dielectric layer containing a hafnium titanium oxide film structured as one or more monolayers include the dielectric layer disposed in an integrated circuit. Embodiments of...
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7572678 |
Methods of making and using a floating lead finger on a lead frame
A semiconductor device assembly includes a semiconductor device and a lead frame having lead fingers for connection to the semiconductor device. The lead frame may include floating no-connect (NC)...
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7572670 |
Methods of forming semiconductor packages
The invention includes semiconductor packages having a patterned substrate with openings extending therethrough, conductive circuit traces over the substrate and having portions extending over the...
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7572572 |
Methods for forming arrays of small, closely spaced features
Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with...
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7572385 |
Method of forming micro-lenses
A method of fabricating micro-lenses is provided. A first layer is formed on a substrate. The first layer is comprised of a first material and the substrate is comprised of a second material. An...
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7570538 |
Method for writing to multiple banks of a memory device
In a multi-bank memory system such as a synchronous dynamic random access memory (SDRAM), a method of writing data to the banks is provided. This method allows for writing to any number of banks....
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7570521 |
Low power flash memory devices
A buried bipolar junction is provided in a floating gate transistor flash memory device. During a write operation electrons are injected into a surface depletion region of the memory cell...
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7570504 |
Device and method to reduce wordline RC time constant in semiconductor memory devices
A semiconductor memory device and a method of making and using a semiconductor memory device containing a word line design, which is used in ultra-large scale integrated (ULSI) circuits, that...
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7570293 |
Image sensor with on-chip semi-column-parallel pipeline ADCS
An imaging device with a semi-column-parallel pipeline analog-to-digital converter architecture. The semi-column-parallel pipeline architecture allows multiple column output lines to share an...
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7570069 |
Resilient contact probes
Carriers comprising a carrier body having a plurality of openings holding a plurality of resilient contact probes are disclosed. A number of different embodiments for the resilient contact probes...
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7569983 |
Flat fluorescent lamp and liquid crystal display using the same
Disclosed herein is a light source device. The light source device includes a front transparent substrate, a rear substrate, a plurality of partitions, and fluorescent material. The rear substrate...
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7569934 |
Copper interconnect
An improved wire bond is provided with the bond pads of semiconductor devices and the lead fingers of lead frames or an improved conductive lead of a TAB tape bond with the bond pad of a...
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7569915 |
Shielding arrangement to protect a circuit from stray magnetic fields
A shielding arrangement for protecting a circuit containing magnetically sensitive materials from external stray magnetic fields. A shield of a material having a relatively high permeability is...
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7569876 |
DRAM arrays, vertical transistor structures, and methods of forming transistor structures and DRAM arrays
The invention includes a method of forming a semiconductor construction. Dopant is implanted into the upper surface of a monocrystalline silicon substrate. The substrate is etched to form a...
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7569485 |
Method for an integrated circuit contact
A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the...
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7569484 |
Plasma and electron beam etching device and method
Methods and devices for selective etching in a semiconductor process are shown. Chemical species generated in a reaction chamber provide both a selective etching function and concurrently form a...
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7569473 |
Methods of forming semiconductor assemblies
Apparatus and methods are disclosed relating to semiconductor assemblies. A semiconductor assembly includes an interposer which may be constructed from a flexible material, such as a polyimide...
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7569468 |
Method for forming a floating gate memory with polysilicon local interconnects
Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming...
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7569453 |
Contact structure
This invention relates to contact structures for use in integrated circuits and methods of fabricating contact structures. In one embodiment, a contact structure includes a conductive layer, one or...
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7569418 |
Methods for securing packaged semiconductor devices to carrier substrates
A method for securing a semiconductor device to a carrier substrate includes inserting a semiconductor device with a plurality of stub contacts extending from a bottom edge thereof into a...
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7569414 |
CMOS imager with integrated non-volatile memory
A CMOS imager and non-volatile memory are integrated on a single substrate along with logic and support circuitry for decoding and processing optical information received by the CMOS imager. A...
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7569311 |
Method of forming a pattern using a polarized reticle in conjunction with polarized light
Polarized reticles, photolithography systems utilizing a polarized reticle, and methods of using such a system are disclosed. A polarized reticle is formed having a reticle containing at least one...
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7568970 |
Chemical mechanical polishing pads
The present invention provides a deformable pad useful for chemical mechanical polishing (“CMP”), a CMP apparatus incorporating the deformable pad of the present invention, and methods for...
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7567848 |
Speaker apparatus and a computer system incorporating same
An internal subwoofer apparatus is provided for mounting within a computer system. The computer system is a multi-media computer system that processes visual and audio recording and playback. The...
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7567477 |
Bias sensing in sense amplifiers through a voltage-coupling/decoupling device
Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices...
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7567472 |
Memory block testing
A memory device is tested by programming a plurality of pages of a memory block of the memory device, determining a programming time for each page, determining a total programming time for the...
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7567465 |
Power saving sensing scheme for solid state memory
Methods and apparatus are disclosed, such as those involving a solid state memory device. One such method includes selecting a plurality of memory cells in a memory array. States of a plurality of...
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7567462 |
Method and system for selectively limiting peak power consumption during programming or erase of non-volatile memory devices
A power supply circuit is used to supply power having a limited peak magnitude to an array of non-volatile memory cells during programming or erasing of the memory cells. The power supply circuit...
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7567461 |
Method and system for minimizing number of programming pulses used to program rows of non-volatile memory cells
A flash memory device programs cells in each row in a manner that minimizes the number of programming pulses that must be applied to the cells during programming. The flash memory device includes a...
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7567455 |
Method and system for programming non-volatile memory cells based on programming of proximate memory cells
A multi-level non-volatile memory device programs cells in each row in a manner that takes into account the coupling from the programming of cells that are proximate the row to be programmed. In...
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7567091 |
Method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer
A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited...
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7566620 |
DRAM including a vertical surround gate transistor
DRAM memory cells having a feature size of less than about 4F2 include vertical surround gate transistors that are configured to reduce any short channel effect on the reduced size memory cells. In...
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