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7579615 |
Access transistor for memory device
An access transistor for a resistance variable memory element and methods of forming the same are provided. The access transistor has first and second source/drain regions and a channel region...
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7579278 |
Topography directed patterning
A pattern having exceptionally small features is formed on a partially fabricated integrated circuit during integrated circuit fabrication. The pattern comprises features formed by self-organizing...
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7579267 |
Methods and systems for fabricating semiconductor components with through wire interconnects (TWI)
A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) bonded to the substrate contact. The through wire interconnect (TWI)...
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7579242 |
High performance multi-level non-volatile memory device
Non-volatile memory devices and arrays are described that utilize band engineered gate-stacks and multiple charge trapping layers allowing a multiple trapping site gate-insulator stack memory cell...
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7579240 |
Method of making vertical transistor with horizontal gate layers
Vertical body transistors with adjacent horizontal gate layers are used to form a memory array in a high density flash electrically erasable and programmable read only memory (EEPROM) or a logic...
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7579235 |
Container capacitor structure and method of formation thereof
Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the...
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7578056 |
Method of coating contacts on a surface of a flip chip
A method for encapsulating a flip chip in one step is disclosed. The flip chip is immersed in a polymer bath to apply a coating of the polymer to the surface of the flip chip except for the distal...
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7577830 |
Peripheral device with hardware linked list
A linked list is implemented in hardware. Various registers within the linked list are writeable until a control register is written, rendering the registers read-only. A computer peripheral...
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7577790 |
Caching of dynamic arrays
Systems and methods are provided for caching dynamic arrays. According to one aspect, a cache memory device is provided for caching dynamic arrays or dynamic overlays. According to one embodiment,...
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7577212 |
Method and system for generating reference voltages for signal receivers
A method and system for generating a reference voltage for memory device signal receivers operates in either a calibration mode or a normal operating mode. In the calibration mode, the magnitude of...
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7577044 |
Resistive memory element sensing using averaging
A system for determining the logic state of a resistive memory cell element, for example an MRAM resistive cell element. The system includes a controlled voltage supply, an electronic charge...
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7577036 |
Non-volatile multilevel memory cells with data read of reference cells
Embodiments of the present disclosure provide methods, devices, modules, and systems for non-volatile multilevel memory cell data retrieval with data read of reference cells. One method includes...
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7577027 |
Multi-state memory cell with asymmetric charge trapping
A multi-state NAND memory cell is comprised of two drain/source areas in a substrate. An oxide-nitride-oxide structure is formed above the substrate between the drain/source areas. The nitride...
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7576441 |
Boron-doped amorphous carbon film for use as a hard etch mask during the formation of a semiconductor device
A hard mask comprising boron-doped amorphous carbon, and a method for forming the hard mask, provides improved resistance to etches of a variety of materials compared with previous amorphous carbon...
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7576400 |
Circuitry and gate stacks
The present invention includes semiconductor circuitry. Such circuitry encompasses a metal silicide layer over a substrate and a layer comprising silicon, nitrogen and oxygen in physical contact...
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7576398 |
Method of composite gate formation
Methods for forming a nitride barrier film layer in semiconductor devices such as gate structures, and barrier layers, semiconductor devices and gate electrodes are provided. The nitride layer is...
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7576380 |
Methods for enhancing capacitors having roughened features to increase charge-storage capacity
Structures and methods for making a semiconductor structure are discussed. The semiconductor structure includes a rough surface having protrusions formed from an undoped silicon film. If the...
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7576378 |
Systems and methods for forming metal oxides using metal diketonates and/or ketoimines
A method of forming (and an apparatus for forming) a metal oxide layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process and one or more...
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7576012 |
Atomic layer deposition methods
A first precursor gas is flowed to the substrate within the chamber effective to form a first monolayer on the substrate. A second precursor gas different in composition from the first precursor...
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7575999 |
Method for creating conductive elements for semiconductor device structures using laser ablation processes and methods of fabricating semiconductor device assemblies
A method for forming at least one conductive element is disclosed. Particularly, a semiconductor substrate, including a plurality of semiconductor dice thereon, may be provided and a dielectric...
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7575978 |
Method for making conductive nanoparticle charge storage element
Isolated conductive nanoparticles on a dielectric layer and methods of fabricating such isolated conductive nanoparticles provide charge storage units in electronic structures for use in a wide...
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7575953 |
Stacked die with a recess in a die BGA package
Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies for increasing semiconductor device density are provided.
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7574634 |
Real time testing using on die termination (ODT) circuit
A system and method to operate an electronic device, such as a memory chip, in a test mode using the device's built-in ODT (on die termination) circuit is disclosed. One or more test mode related...
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7573752 |
NAND flash memory cell programming
A flash memory device, such as a NAND flash, is described having an array of floating gate transistor memory cells arranged in a first and second addressable blocks. A voltage source to supply...
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7573738 |
Mode selection in a flash memory device
A single flash memory device has selectable read modes for either a segment mode or a page mode. The desired mode is selected by writing a control word to a mode control register. Selecting the...
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7573733 |
Self-identifying stacked die semiconductor components
A semiconductor die having a functional circuit (e.g., a memory array) and a decode circuit suitable for use in a stacked die semiconductor component (e.g., a random access memory component) is...
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7573288 |
Dynamically adjusting operation of a circuit within a semiconductor device
Systems and methods for dynamically adjusting operation of a circuit within a semiconductor device are described herein. At least some illustrative embodiments include a system that includes a...
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7573276 |
Probe card layout
Multi-touchdown, parallel test probe cards having probe elements arranged to provide greater than 99% efficiency during testing of a substrate having a plurality of die thereon, and methods of use.
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7573136 |
Semiconductor device assemblies and packages including multiple semiconductor device components
A multidie semiconductor device assembly or package includes an interposer comprising a substrate with at least one receptacle therethrough. A plurality of semiconductor device components (e.g.,...
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7573125 |
Methods for reducing stress in microelectronic devices and microelectronic devices formed using such methods
Methods for reducing stress in microelectronic devices and microelectronic devices formed using such methods are disclosed herein. One such device can include a first support member, a second...
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7573121 |
Method for enhancing electrode surface area in DRAM cell capacitors
Methods for forming the lower electrode of a capacitor in a semiconductor circuit, and the capacitors formed by such methods are provided. The lower electrode is fabricated by forming a texturizing...
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7573116 |
Etch aided by electrically shorting upper and lower sidewall portions during the formation of a semiconductor device
A method used to fabricate a semiconductor device comprises etching a dielectric layer, resulting in an undesirable charge buildup along a sidewall formed in the dielectric layer during the etch....
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7573108 |
Non-planar transistor and techniques for fabricating the same
A non-planar transistor and methods for fabricating the same. In certain embodiments, the transistor includes an active gate and a passive gate. The active gate may be switchably coupled to a first...
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7573088 |
DRAM array and electronic system
The invention includes a semiconductor construction including rows of contact plugs, and rows of parallel bottom plates. The plug pitch is approximately double the plate pitch. The invention...
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7573087 |
Interconnect line selectively isolated from an underlying contact plug
A means for selectively electrically connecting an electrical interconnect line, such as a bit line of a memory cell, with an associated contact stud and electrically isolating the interconnect...
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7573021 |
Method and apparatus for multiple scan rate swept wavelength laser-based optical sensor interrogation system with optical path length measurement capability
The invention relates to optical sensor measurement methods that use a swept wavelength optical source to determine wavelength shift as well as to optical sensor systems that embody and employ...
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7573006 |
Apparatus relating to the reconstruction of semiconductor wafers for wafer-level processing
Apparatus, systems and methods relating to the reconstruction of semiconductor wafers for wafer-level processing are disclosed. Selected semiconductor dice having alignment cavities formed in a...
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7572731 |
Unsymmetrical ligand sources, reduced symmetry metal-containing compounds, and systems and methods including same
The present invention provides metal-containing compounds that include at least one β-diketiminate ligand, and methods of making and using the same. In some embodiments, the metal-containing...
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7572710 |
Methods of forming conductive contacts to source/drain regions and methods of forming local interconnects
The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local interconnects. In one implementation, a method of...
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7572695 |
Hafnium titanium oxide films
Embodiments of a dielectric layer containing a hafnium titanium oxide film structured as one or more monolayers include the dielectric layer disposed in an integrated circuit. Embodiments of...
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7572678 |
Methods of making and using a floating lead finger on a lead frame
A semiconductor device assembly includes a semiconductor device and a lead frame having lead fingers for connection to the semiconductor device. The lead frame may include floating no-connect (NC)...
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7572670 |
Methods of forming semiconductor packages
The invention includes semiconductor packages having a patterned substrate with openings extending therethrough, conductive circuit traces over the substrate and having portions extending over the...
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7572572 |
Methods for forming arrays of small, closely spaced features
Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with...
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7572385 |
Method of forming micro-lenses
A method of fabricating micro-lenses is provided. A first layer is formed on a substrate. The first layer is comprised of a first material and the substrate is comprised of a second material. An...
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7570538 |
Method for writing to multiple banks of a memory device
In a multi-bank memory system such as a synchronous dynamic random access memory (SDRAM), a method of writing data to the banks is provided. This method allows for writing to any number of banks....
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7570521 |
Low power flash memory devices
A buried bipolar junction is provided in a floating gate transistor flash memory device. During a write operation electrons are injected into a surface depletion region of the memory cell...
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7570504 |
Device and method to reduce wordline RC time constant in semiconductor memory devices
A semiconductor memory device and a method of making and using a semiconductor memory device containing a word line design, which is used in ultra-large scale integrated (ULSI) circuits, that...
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7570293 |
Image sensor with on-chip semi-column-parallel pipeline ADCS
An imaging device with a semi-column-parallel pipeline analog-to-digital converter architecture. The semi-column-parallel pipeline architecture allows multiple column output lines to share an...
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7570069 |
Resilient contact probes
Carriers comprising a carrier body having a plurality of openings holding a plurality of resilient contact probes are disclosed. A number of different embodiments for the resilient contact probes...
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7569983 |
Flat fluorescent lamp and liquid crystal display using the same
Disclosed herein is a light source device. The light source device includes a front transparent substrate, a rear substrate, a plurality of partitions, and fluorescent material. The rear substrate...
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