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7345332 Semiconductor constructions  
The invention includes a method of forming a planarized surface over a semiconductor substrate. A substrate is provided which includes a memory array region and a peripheral region proximate the...
7345299 Semiconductor device comprising a crystalline layer containing silicon/germanium, and comprising a silicon Enriched floating charge trapping media over the crystalline layer  
The invention includes non-volatile memory and logic devices associated with crystalline Si/Ge. The devices can include TFT constructions. The non-volatile devices include a floating gate or...
7345269 Method and apparatus providing configurable current source device for image sensors with a selective current at an output node  
A configurable current source for imager readout system that can be operated as a simple-current-source or as a cascode-current-source. The configurable current source can be operated in a...
7344977 Method of electroplating a substance over a semiconductor substrate  
The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate having defined first and second...
7344975 Method to reduce charge buildup during high aspect ratio contact etch  
A method of high aspect ratio contact etching a substantially vertical contact hole in an oxide layer using a hard photoresist mask is described. The oxide layer is deposited on an underlying...
7344969 Stacked die in die BGA package  
Semiconductor devices and stacked die assemblies, and methods of fabrication are provided. In various embodiments, the die assembly comprises a first die mounted on a substrate and a second die...
7344948 Methods of forming transistors  
The invention encompasses a method of incorporating nitrogen into a silicon-oxide-containing layer. The silicon-oxide-containing layer is exposed to a nitrogen-containing plasma to introduce...
7344946 Structure for amorphous carbon based non-volatile memory  
A memory device including at least one first memory element comprising a first layer of amorphous carbon over at least one second memory element comprising a second layer of amorphous carbon. The...
7344942 Isolation regions for semiconductor devices and their formation  
A hard mask layer is formed and patterned overlying a semiconductor substrate of a semiconductor device. The patterned hard mask layer exposes two or more areas of the substrate for future...
7344937 Methods and apparatus with silicide on conductive structures  
Exemplary embodiments of the invention provide pixel circuits having transistors with silicide on top of their gate stacks. In the exemplary embodiments, silicide forming material does not...
7344921 Integrated circuit device having reduced bow and method for making same  
An integrated circuit device includes a semiconductor component coupled with a lead frame, and an integrated circuit package encompassing at least a portion of the semiconductor component. The...
7344899 Die assembly and method for forming a die on a wafer  
A method for forming a die on a wafer is provided. The method includes forming on a wafer a die having an active portion that includes integrated circuitry. The method further includes forming at...
7344755 Methods and apparatus for processing microfeature workpieces; methods for conditioning ALD reaction chambers  
The present disclosure provides methods and apparatus that may be used to process microfeature workpieces, e.g., semiconductor wafers. Some aspects have particular utility in depositing TiN in a...
7344061 Multi-functional solder and articles made therewith, such as microelectronic components  
Aspects of the invention provide solder compositions which include two different fluxing agents. One of the fluxing agents promotes melting of a metal of the solder at a first activation...
7343444 Reconfigurable memory module and method  
A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory...
7342409 System for testing semiconductor components  
A system for testing semiconductor components includes an interconnect, an alignment system for aligning a substrate to the interconnect, a bonding system for bonding the component to the...
7342319 Semiconductor integrated circuit package having electrically disconnected solder balls for mounting  
Integrated circuit packages that connect solder balls between solder ball pads of a die and substrate pads of a printed circuit board (PCB). The solder balls are electrically disconnected from any...
7342273 Applying epitaxial silicon in disposable spacer flow  
A process for forming active transistors for a semiconductor memory device by the steps of: forming transistor gates having generally vertical sidewalls in a memory array section and in periphery...
7342272 Flash memory with recessed floating gate  
A flash memory device where the floating gate of the flash memory is defined by a recessed access device. The use of a recessed access device results in a longer channel length with less loss of...
7342212 Analog vertical sub-sampling in an active pixel sensor (APS) image sensor  
An active pixel sensor (APS) image sensor comprises an array of pixel circuits corresponding to rows and columns of pixels, a plurality of amplifiers that buffer signals output by the array of...
7341957 Masking structure having multiple layers including amorphous carbon layer  
A masking structure having multiple layers is formed. The masking structure includes an amorphous carbon layer and a cap layer formed over the amorphous carbon layer. The amorphous carbon layer...
7341951 Methods of forming semiconductor constructions  
The invention includes methods of forming semiconductor constructions in which a single etch is utilized to penetrate through a titanium-containing layer and partially into a silicon-containing...
7341947 Methods of forming metal-containing films over surfaces of semiconductor substrates  
The invention includes a method of forming a metal-containing film over a surface of a semiconductor substrate. The surface is exposed to a supercritical fluid. The supercritical fluid has H 2 , at...
7341931 Methods of forming low resistivity contact for an integrated circuit device  
Contact areas comprising doped semiconductor material at the bottom of contact holes are cleaned in a hot hydrogen plasma and exposed in situ during and/or separately from the hot hydrogen clean to...
7341909 Methods of forming semiconductor constructions  
The invention includes methods of forming semiconductor constructions in which electrically conductive structures are formed between bitlines to electrically connect with storage node contacts. The...
7341906 Method of manufacturing sidewall spacers on a memory device, and device comprising same  
The present invention is generally directed to a method of manufacturing sidewall spacers on a memory device, and a memory device comprising such sidewall spacers. In one illustrative embodiment,...
7341901 Semiconductor processing methods of forming integrated circuitry  
Semiconductor processing methods of forming integrated circuitry are described. In one embodiment, memory circuitry and peripheral circuitry are formed over a substrate. The peripheral circuitry...
7341881 Methods of packaging and testing microelectronic imaging devices  
Microelectronic imaging devices and methods of packaging microelectronic imaging devices are disclosed herein. In one embodiment, a microelectronic imaging device includes a microelectronic die...
7341502 Methods and systems for planarizing workpieces, e.g., microelectronic workpieces  
Planarizing workpieces, e.g., microelectronic workpieces, can employ a process indicator which is adapted to change an optical property in response to a planarizing condition. This process...
RE40137 Methods for forming integrated circuits within substrates  
The invention includes methods for forming integrated circuits within substrates, and embedded circuits. In one aspect, the invention includes a method of forming an integrated circuit within a...
7340668 Low power cost-effective ECC memory system and method  
A memory controller couples 32-bit data words to and from a DRAM. The DRAM generates error checking and correcting syndromes to check and correct read data. The DRAM generates the syndromes from...
7340584 Sequential nibble burst ordering for data  
A combination of circuits for use in a memory device is comprised of a decode circuit responsive to a first portion of address information for identifying a word to be read or written. The decode...
7339839 Triggering of IO equilibrating ending signal with firing of column access signal  
A method and apparatus for improving time between row address latching and column address latching (tRCD) by allowing the pull-up of the IO lines during a READ burst to end upon the firing of a...
7339838 Method and apparatus for supplementary command bus  
An electronic system according to various aspects of the present invention includes a memory having a location-specific command interface and a general command interface. The memory communicates...
7339830 One transistor SOI non-volatile random access memory cell  
Various semiconductor structure embodiments include a substrate, a buried insulator over at least a portion of the substrate, a body region over the buried insulator, first and second source/drain...
7339818 Spintronic devices with integrated transistors  
The semiconductor industry seeks to replace traditional volatile memory devices with improved non-volatile memory devices. The increased demand for a significantly advanced, efficient, and...
7339812 Stacked 1T-nmemory cell structure  
This invention relates to memory technology and new variations on memory array architecture to incorporate certain advantages from both cross-point and 1T-1Cell architectures. The fast read-time...
7339811 Stacked columnar 1T-nMTJ MRAM structure and its method of formation and operation  
This invention relates to an MRAM array architecture which incorporates certain advantages from both cross-point and 1T-1MTJ architectures during reading operations. The fast read-time and higher...
7339431 CMOS amplifiers with frequency compensating capacitors  
The frequency and transient responses of a CMOS differential amplifier are improved by employing one or more compensating capacitors. A compensating capacitor coupled to a differential input of the...
7339423 Technique to improve the gain and signal to noise ratio in CMOS switched capacitor amplifiers  
The present invention comprises switched capacitor amplifiers including positive feedback on semiconductor devices, wafers, and systems incorporating same and methods for amplifying signals using...
7339408 Generating multi-phase clock signals using hierarchical delays  
Circuits and methods for generating multi-phase clock signals using digitally-controlled hierarchical delay units (HDs) are provided. A plurality of serially-coupled HDs outputs clock signals that...
7339239 Vertical NROM NAND flash memory array  
Memory devices, arrays, and strings are described that facilitate the use of NROM memory cells in NAND architecture memory strings, arrays, and devices. NROM NAND architecture memory embodiments of...
7339228 Non-planar flash memory array with shielded floating gates on silicon mesas  
A first plane of memory cells is formed on mesas of the array. A second plane of memory cells is formed in valleys adjacent to the mesas. The second plurality of memory cells is coupled to the...
7339217 High dynamic range image sensor  
A pixel cell with controlled leakage is formed by modifying the location and gate profile of a high dynamic range (HDR) transistor. The HDR transistor may have a dual purpose, acting as both a...
7339191 Capacitors having doped aluminum oxide dielectrics  
Doped aluminum oxide layers having a porous aluminum oxide layer and methods of their fabrication. The porous aluminum oxide layer may be formed by evaporation physical vapor deposition techniques...
7338889 Method of improving copper interconnects of semiconductor devices for bonding  
An improved wire bond is provided with the bond pads of semiconductor devices and the lead fingers of lead frames or an improved conductive lead of a TAB tape bond with the bond pad of a...
7338866 Strapping word lines of NAND memory devices  
Conductive straps are connected to a subset of word lines of a memory device. Alternatively, first conductive straps are respectively connected only to first portions of first word lines of a...
7338856 Double-doped polysilicon floating gate  
The present invention provides a method and apparatus for forming a double-doped polysilicon floating gate in a semiconductor memory element. The method includes forming a first dielectric layer on...
7338851 Diode/superionic conductor/polymer memory structure  
A conjugated polymer layer with a built-in diode is formed by providing a first metal-chalcogenide layer over a bottom electrode. Subsequently, a second metal-chalcogenide layer is provided over...
7338609 Partial edge bead removal to allow improved grounding during e-beam mask writing  
A method to provide a ground point for second, or subsequent, e-beam mask-writing steps by selectively removing the photoresist edge bead of a photomask substrate to expose the underlying chrome...
Matches 251 - 300 out of 16945 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >