Matches 201 - 250 out of 16945 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >
Match Document Document Title
7352603 Apparatus and methods for optically-coupled memory systems  
Optically-coupled memory systems are disclosed. In one embodiment, a system memory includes a carrier substrate, and a controller attached to the carrier substrate and operable to transmit and...
7352602 Configurable inputs and outputs for memory stacking system and method  
Embodiments of the present invention relate to configurable inputs and/or outputs for memory and memory stacking applications. More specifically, embodiments of the present invention include memory...
7352511 Micro-lenses for imagers  
A micro-lens and a method for forming the micro-lens is provided. A micro-lens includes a substrate and lens material located within the substrate, the substrate having a recessed area serving as a...
7352201 System and method for testing devices utilizing capacitively coupled signaling  
An apparatus and method for testing a semiconductor device in an AC test regime. The test apparatus includes a test plate capacitively couple to the signal terminals of the integrated circuit. The...
7352023 Constructions comprising hafnium oxide  
The invention includes methods of forming hafnium-containing materials, such as, for example, hafnium oxide. In one aspect, a semiconductor substrate is provided, and first reaction conditions are...
7352019 Capacitance reduction by tunnel formation for use with a semiconductor device  
A method used during the manufacture of a semiconductor device comprises providing at least first, second, and third spaced conductive structures, where the second conductive structure is...
7352007 Phosphorescent nanotube memory device  
An optical memory cell having a material layer associated with a pixel capable of emitting and receiving light. The material layer has phosphorescent material formed therein for storing data as...
7351945 Alignment among elements in an image sensor  
An image sensor is formed with shifts among the optical parts of the sensor and the photosensitive parts of the sensor. The optical parts of the sensor may include a color filter array and/or...
7351659 Methods of forming a transistor with an integrated metal silicide gate electrode  
Methods of forming a transistor having integrated metal silicide transistor gate electrode on a semiconductor assembly are described. The transistor gate is partially fabricated by reacting the...
7351640 Methods of fabricating double-sided hemispherical silicon grain electrodes and capacitor modules  
Methods are provided for robust and cost effective techniques to fabricate a semiconductor device having double-sided hemispherical silicon grain (HSG) electrodes for container capacitors. In an...
7351628 Atomic layer deposition of CMOS gates with variable work functions  
Structures, systems and methods for transistors having gates with variable work functions formed by atomic layer deposition are provided. One transistor embodiment includes a first source/drain...
7351620 Methods of forming semiconductor constructions  
The invention includes BIFETRAM devices. Such devices comprise a bipolar transistor in combination with a field effect transistor (FET) in a three-dimensional stacked configuration. The memory...
7350182 Methods of forming patterned reticles  
The invention includes methods of forming patterned reticles. Design features can be introduced into a layout for a reticle prior to optical proximity correction, and then removed prior to taping a...
7350093 Apparatus and method for generating a delayed clock signal  
An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal from an input clock...
7350044 Data move method and apparatus  
An improved Flash memory device, control circuit, or data handling methods is described that facilitate the moving and consolidating data in split and non-split user/overhead data sector...
7350018 Method and system for using dynamic random access memory as cache memory  
A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In...
7349277 Method and system for reducing the peak current in refreshing dynamic random access memory devices  
A dynamic random access memory device includes a mode register that is programmed with a delay value. In some embodiments, a offset code is also stored in the memory device. The memory device uses...
7349273 Access circuit and method for allowing external test voltage to be applied to isolated wells  
An access circuit selectively couples an externally accessible terminal to each of a plurality of isolated DRAM wells in which respective DRAM arrays are fabricated. The access circuit for each...
7349270 Semiconductor memory with wordline timing  
A semiconductor memory with wordline timing, which links activating a wordline to an isolation signal. The isolation signal is applied to a memory section adjacent the memory section containing the...
7349269 Programmable DQS preamble  
A method and apparatus for programming a data strobe (DQS) preamble in a memory by loading a defined set of bits into one or more registers of the memory, where one or more bits are formatted...
7349252 Integrated DRAM-NVRAM multi-level memory  
An integrated DRAM-NVRAM, multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate floating plate device. The floating plate device provides enhanced charge...
7349232 6F2 DRAM cell design with 3F-pitch folded digitline sense amplifier  
The present invention is generally directed to a DRAM cell design with folded digitline sense amplifier. In one illustrative embodiment, a memory array having a plurality of memory cells having an...
7348674 Low capacitance wiring layout  
Integrated circuits having multi-level wiring layouts designed to inhibit the capacitive-resistance effect, and a method for fabricating such integrated circuits, is described. The integrated...
7348671 Vias having varying diameters and fills for use with a semiconductor device and methods of forming semiconductor device structures including same  
A method for forming electrical interconnects having different diameters and filler materials through a semiconductor wafer comprises forming first and second openings through a semiconductor,...
7348652 Bulk-isolated PN diode and method of forming a bulk-isolated PN diode  
A technique for making a bulk isolated PN diode. Specifically, a technique is provided for making a voltage clamp with a pair of bulk isolated PN diode. Another embodiment provides for a voltage...
7348613 CMOS imager with selectively silicided gates  
The invention also relates to an apparatus and method for selectively providing a silicide coating over the transistor gates of a CMOS imager to improve the speed of the transistor gates. The...
7348238 Bottom electrode for memory device and method of forming the same  
Contacts having use in an integrated circuit and exemplary methods of forming the contacts are disclosed. The methods involve forming a conductive cap over a metal plug. The invention can mitigate...
7348237 NOR flash memory cell with high storage density  
Structures and methods for NOR flash memory cells, arrays and systems are provided. The NOR flash memory cell includes a vertical floating gate transistor extending outwardly from a substrate. The...
7348236 Formation of memory cells and select gates of NAND memory arrays  
Apparatus and methods are provided. Floating-gate memory cells and select gates of NAND memory arrays are formed concurrently by anisotropically removing portions of a second conductive layer...
7348234 Methods of forming capacitor constructions  
The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate having defined first and second...
7348215 Methods for assembly and packaging of flip chip configured dice with interposer  
A method for assembly and packaging of one or more flip chip-configured semiconductor dice with an interposer substrate to form a flip chip-type semiconductor device assembly. The flip chip-type...
7348213 Method for forming component mounting hole in semiconductor substrate  
The present invention provides to a substrate for a semiconductor device, in which electric characteristics to high-speed signals are enhanced by facilitating the mounting of a circuit component,...
7348209 Resistance variable memory device and method of fabrication  
Methods and apparatus for providing a resistance variable memory device with agglomeration prevention and thermal stability. According to one embodiment, a resistance variable memory device is...
7348205 Method of forming resistance variable devices  
A method of forming a resistance variable device includes forming a first conductive electrode material on a substrate. A metal doped chalcogenide comprising material is formed over the first...
7347767 Retaining rings, and associated planarizing apparatuses, and related methods for planarizing micro-device workpieces  
Retaining rings and associated planarizing apparatuses, and related methods for planarizing micro-device workpieces are disclosed herein. A carrier head configured in accordance with one embodiment...
7347349 Apparatus and method for printing micro metal structures  
A method and device for printing liquid material such as liquid solder is provided. C4 structures as small as 10 microns in diameter can be produced using devices and methods described above....
7347348 Apparatus and method for depositing and reflowing solder paste on a microelectronic workpiece  
Stenciling machines and methods for forming solder balls on microelectronic workpieces are disclosed herein. In one embodiment, a method for depositing and reflowing solder paste on a...
7346818 Method and apparatus for redundant location addressing using data compression  
A method and apparatus for identifying defective cells in a memory array includes receiving a request for accessing an address and analyzing the address to determine when the address matches an...
7346817 Method and apparatus for generating and detecting initialization patterns for high speed DRAM systems  
A method and apparatus for determining the characteristics of a communications channel within a high speed memory system includes generating a first signal having a known and repeating pattern and...
7346162 Public key cryptography using matrices  
The invention provides techniques for secure messages transmission using a public key system to exchange secret keys. A first entity creates public and private keys by generating a product n of two...
7345937 Open digit line array architecture for a memory array  
A system and method for sensing a data state stored by a memory cell that includes coupling a first digit line and a second digit line to a precharge voltage and further coupling a memory cell to...
7345932 Low power dissipation voltage generator  
A voltage generator circuit is described for providing a regulated voltage, such as a negative word line voltage in a semiconductor memory. The generator uses a source transistor to couple a...
7345924 Programming memory devices  
A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is...
7345922 Position based erase verification levels in a flash memory device  
The location of a cell to be erase verified is determined. The erase verification threshold voltage is then set. The threshold voltage is changed in response to the cell's location with respect to...
7345918 Selective threshold voltage verification and compaction  
Non-volatile memory devices for providing selective compaction verification and/or selective compaction to facilitate a tightening of the distribution of threshold voltages in memory devices...
7345575 Radio frequency data communications device with adjustable receiver sensitivity and method  
A device has a monolithic semiconductor integrated circuit with integrated circuitry, interrogation receiving circuitry provided on the monolithic integrated circuit forming at least part of the...
7345515 Low power and low timing jitter phase-lock loop and method  
A phase-lock loop generates an output clock signal from an input clock signal. The output clock signal is coupled through a clock tree and is fed back to a phase detector, which compares the phase...
7345358 Copper interconnect for semiconductor device  
An improved wire bond is provided with the bond pads of semiconductor devices and the lead fingers of lead frames or an improved conductive lead of a TAB tape bond with the bond pad of a...
7345350 Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias  
A method for forming a conductive via in a semiconductor component is disclosed. The method includes providing a substrate having a first surface and an opposing, second surface. At least one hole...
7345333 Double sided container process used during the manufacture of a semiconductor device  
A method used during the formation of a semiconductor device comprises providing a wafer substrate assembly comprising a plurality of digit line plug contact pads and capacitor storage cell contact...
Matches 201 - 250 out of 16945 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >