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7365784 Column sample-and-hold cell for CMOS APS sensor  
A sample and hold readout circuit and method of operation which minimizes fixed pattern noise during a read out operation. The circuit improves the consistency of the pixel to pixel output of the...
7365773 CMOS APS with stacked avalanche multiplication layer and low voltage readout electronics  
An image sensor includes a pixel having a protection circuit connected to a charge multiplying photoconversion layer. The protection circuit prevents the pixel circuit from breaking down when the...
7365597 Switched capacitor amplifier with higher gain and improved closed-loop gain accuracy  
A switched capacitor CMOS amplifier uses a first stage non-inverting CMOS amplifier driving a second stage inverting CMOS amplifier. The first stage amplifier is provided with positive feedback to...
7365570 Pseudo-differential output driver with high immunity to noise and jitter  
Circuits and methods are provided for transmitting a pseudo-differential output signal with relatively high immunity to noise and jitter. The output driver of the invention receives two...
7365558 In-tray burn-in board, device and test assembly for testing integrated circuit devices in situ on processing trays  
A burn-in board for burn-in and electrical testing of a plurality of integrated circuit devices that is disposed in one or more processing trays may include a substrate having an interface surface...
7365424 Microelectronic component assemblies with recessed wire bonds and methods of making same  
The present disclosure suggests various microelectronic component assembly designs and methods for manufacturing microelectronic component assemblies. In one particular implementation, a...
7365420 Semiconductor packages and methods for making and using same  
A semiconductor package is provided which includes a substrate having a plurality of semiconductor dice mounted thereon. The substrate is divided into segments by grooves formed in the bottom...
7365411 Resistance variable memory with temperature tolerant materials  
A PCRAM memory device having a chalcogenide glass layer, preferably comprising antimony selenide having a stoichiometric formula of about Sb 2 Se 3 , and a metal-chalcogenide layer and methods of...
7365409 Two-transistor pixel with buried reset channel and method of formation  
A two-transistor pixel of an imager has a reset region formed adjacent a charge collection region of a photodiode and in electrical communication with a gate of a source follower transistor. The...
7365388 Embedded trap direct tunnel non-volatile memory  
The cell comprises a substrate having a drain region and a source region. An oxynitride layer is formed over the substrate. An embedded trap layer is formed over the oxynitride layer. An injector...
7365385 DRAM layout with vertical FETs and method of formation  
DRAM cell arrays having a cell area of less than about 4F 2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a...
7365384 Trench buried bit line memory devices and methods thereof  
A memory device includes isolation trenches that are formed generally parallel to and along associated strips of active area. A conductive bit line is recessed within each isolation trench such...
7365305 Layered lens structures and methods of production in which radius of curvature of the upper lens can be varied  
A microlens structure includes lower lens layers on a substrate. A sputtered layer of glass, such as silicon oxide, is applied over the lower lens layers at an angle away from normal to form upper...
7365028 Methods of forming metal oxide and semimetal oxide  
The invention includes methods of forming metal oxide and/or semimetal oxide. The invention can include formation of at least one metal-and-halogen-containing material and/or at least one...
7365027 ALD of amorphous lanthanide doped TiOx films  
The use of atomic layer deposition (ALD) to form an amorphous dielectric layer of titanium oxide (TiO x ) doped with lanthanide elements, such as samarium, europium, gadolinium, holmium, erbium and...
7364997 Methods of forming integrated circuitry and methods of forming local interconnects  
In one implementation, field oxide is grown within bulk semiconductive material in a first circuitry area and not over immediately adjacent bulk semiconductive material in a second circuitry area....
7364985 Method for creating electrical pathways for semiconductor device structures using laser machining processes  
A method for creating electrical pathways for semiconductor device structures using laser machining processes is provided. The method of the present invention includes providing a semiconductor...
7364981 Methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating memory circuitry, integrated circuitry and memory integrated circuitry  
The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including memory circuitry, and integrated...
7364966 Method for forming a buried digit line with self aligning spacing layer and contact plugs during the formation of a semiconductor device, semiconductor devices, and systems including same  
A method for use during fabrication of a semiconductor device comprises the formation of buried digit lines and contacts. During formation, a buried bit line layer may be used as a mask to etch one...
7364934 Microelectronic imaging units and methods of manufacturing microelectronic imaging units  
Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one embodiment, a method for manufacturing a...
7364644 Silver selenide film stoichiometry and morphology control in sputter deposition  
A method of sputter depositing silver selenide and controlling the stoichiometry and nodular defect formations of a sputter deposited silver-selenide film. The method includes depositing...
7363694 Method of testing using compliant contact structures, contactor cards and test system  
A compliant contact structure and contactor card for operably coupling with a semiconductor device to be tested includes a substantially planar substrate with a compliant contact formed therein....
7363452 Pipelined burst memory access  
A memory device for multichannel continuous or fixed burst mode operation includes multiple burst address counter circuits and associated control logic to minimize latency which would otherwise...
7363419 Method and system for terminating write commands in a hub-based memory system  
A memory hub receives downstream memory commands and processes each received downstream memory command to determine whether the memory command includes a write command directed to the memory hub....
7362641 Method and system for low power refresh of dynamic random access memories  
A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data bit is stored in a single memory...
7362637 Current switching sensor detector  
A sensor for a switching circuit detects the logical state of the switching circuit by monitoring the current flow through the switching circuit. The current flow is conditioned by one or more...
7362634 Built-in system and method for testing integrated circuit timing parameters  
A built-in self-test system for a dynamic random access memory device using a data output register of the memory device to apply test signals to data bus terminals and a data strobe terminal of the...
7362627 Method and apparatus for synchronizing data from memory arrays  
According to one embodiment, a combination is comprised of a plurality of sense amps, each having an input for receiving a clock signal. A data bus is for receiving data from the plurality of sense...
7362619 Data strobe synchronization circuit and method for double data rate, multi-bit writes  
A data strobe synchronization circuit includes first and second logic circuits receiving global data strobe pulses and respective enable signal. A control circuit initially applies an enable signal...
7362611 Non-volatile memory copy back  
Data move operations in a memory device are described that enable identification of data errors. During a write operation, identified errors are flagged and used to provide an error status during...
7362113 Universal wafer carrier for wafer level die burn-in  
A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consists of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer,...
7362111 Device for evaluating at least one electrical conducting structure of an electronic component  
An apparatus and method for evaluating the integrity of each contact pin of an electronic component having multiple contact pins. In one embodiment, the apparatus includes a test device and a...
7361928 Doped aluminum oxide dielectrics  
Doped aluminum oxide layers having a porous aluminum oxide layer and methods of their fabrication. The porous aluminum oxide layer may be formed by evaporation physical vapor deposition techniques...
7361862 Laser marking system for dice carried in trays and method of operation  
A laser marking system for IC packages including a tray input shuttle assembly and a tray transport borne by a transport actuator for moving a tray carrier carrying a tray of unmarked packaged ICs...
7361614 Method of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry  
This invention includes methods of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry, and to methods of forming trench isolation in the fabrication of...
7361596 Semiconductor processing methods  
The invention includes methods of forming titanium-containing materials, such as, for example, titanium silicide. The invention can use alternating cycles of titanium halide precursor and one or...
7361569 Methods for increasing photo-alignment margins  
Methods and structures are provided for increasing alignment margins when contacting pitch multiplied interconnect lines with other conductive features in memory devices. The portions of the lines...
7361559 Manufacturing method for a MOS transistor comprising layered relaxed and strained SiGe layers as a channel region  
The invention includes non-volatile memory and logic devices associated with crystalline Si/Ge. The devices can include TFT constructions. The non-volatile devices include a floating gate or...
7361234 Photolithographic stepper and/or scanner machines including cleaning devices and methods of cleaning photolithographic stepper and/or scanner machines  
Stepper and/or scanner machines including cleaning devices and methods for cleaning stepper and/or scanner machines are disclosed herein. In one embodiment, a stepper and/or scanner machine...
7361078 Subpad support with releasable subpad securing element and polishing apparatus  
A subpad support for use in a web format or belt format polishing apparatus for polishing one or more layers of semiconductor device structures. The subpad support includes a subpad retention...
D566709 Storage device  
7360011 Memory hub and method for memory system performance monitoring  
A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics-for example, page hit rate,...
7360006 Apparatus and method for managing voltage buses  
The present technique relates to a method and apparatus for managing voltage buses. In a memory device, such as SRAM or DRAM, a periphery voltage bus may supply voltage to periphery circuitry and...
7359607 Waveguide for thermo optic device  
A waveguide and resonator are formed on a lower cladding of a thermo optic device, each having a formation height that is substantially equal. Thereafter, the formation height of the waveguide is...
7359258 Semiconductor memory with wordline timing  
A semiconductor memory with wordline timing, which links activating a wordline to an isolation signal. The isolation signal is applied to a memory section adjacent the memory section containing the...
7359243 Memory cell repair using fuse programming method in a flash memory device  
A method for repairing cells of a flash memory array includes using a fuse memory array circuit. The fuse memory cells are initially programmed. The locations of defective memory cells of the main...
7359241 In-service reconfigurable DRAM and flash memory device  
A memory cell that has both a DRAM cell and a non-volatile memory cell. The non-volatile memory cell might include a flash memory or an NROM cell. The memory cell is comprised of a vertical...
7358872 Method and apparatus for converting parallel data to serial data in high speed applications  
A method and apparatus to convert parallel data to serial data. More specifically, there is provided a parallel-to-serial converter comprising a data pipeline configured to receive parallel data,...
7358751 Contact pin assembly and contactor card  
A compliant contact pin assembly and a contactor card system are provided. The compliant contact pin assembly includes a contact pin formed from a portion of a substrate with the contact pin...
7358596 Device isolation for semiconductor devices  
Exemplary embodiments of the present invention disclose a semiconductor assembly having at least one isolation structure formed. The semiconductor assembly comprises: a first trench in a...
Matches 101 - 150 out of 16945 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >