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7268388 |
One-transistor composite-gate memory
One-transistor memory devices facilitate nonvolatile data storage through the manipulation of oxygen vacancies within a trapping layer of a field-effect transistor (FET), thereby providing control...
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7268384 |
Semiconductor substrate having first and second pairs of word lines
The invention includes methods of forming memory circuitry. In one implementation, a semiconductor substrate includes a pair of word lines having a bit node received therebetween. A bit node...
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7268382 |
DRAM cells
The invention includes a method of forming a rugged semiconductor-containing surface. A first semiconductor layer is formed over a substrate, and a second semiconductor layer is formed over the...
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7268078 |
Chemical vapor deposition of titanium from titanium tetrachloride and hydrocarbon reactants
A process for depositing titanium metal layers via chemical vapor deposition is disclosed. The process provides deposited titanium layers having a high degree of conformality, even in trenches and...
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7268072 |
Method and structure for reducing contact aspect ratios
An intermediate metal plug is used to raise the platform to which contact is to be made. In the illustrated process, a partial bit line plug is formed adjacent a stacked capacitor, and an...
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7268067 |
Semiconductor integrated circuit package having electrically disconnected solder balls for mounting
Integrated circuit packages that connect solder balls between solder ball pads of a die and substrate pads of a printed circuit board (PCB). The solder balls are electrically disconnected from any...
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7268059 |
Methods for securing components of semiconductor device assemblies to each other with adhesive materials that include pressure-sensitive and curable components
A method for securing a semiconductor device component to another element is provided. An adhesive material includes a pressure-sensitive component and a curable component is used to at least...
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7268057 |
Methods of filling openings with oxide, and methods of forming trenched isolation regions
The invention includes methods in which oxide is formed within openings in a three-step process. A first step is deposition of oxide under a pressure of greater than 15 mTorr. A second step is...
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7268054 |
Methods for increasing photo-alignment margins
Methods and structures are provided for increasing alignment margins when contacting pitch multiplied interconnect lines with other conductive features in memory devices. The portions of the lines...
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7268039 |
Method of forming a contact using a sacrificial structure
A method of forming a double-sided capacitor using at least one sacrificial structure, such as a sacrificial liner or a sacrificial plug. A sacrificial liner is formed along sidewalls of at least...
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7268035 |
Methods of forming semiconductor constructions comprising cerium oxide and titanium oxide
The invention includes semiconductor constructions comprising dielectric materials which contain cerium oxide and titanium oxide. The dielectric materials can contain a homogeneous distribution of...
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7268034 |
Methods of forming pluralities of capacitors, and integrated circuitry
A method of forming a plurality of capacitors includes providing a plurality of capacitor electrodes comprising sidewalls. The plurality of capacitor electrodes are supported at least in part with...
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7268031 |
Memory device with high dielectric constant gate dielectrics and metal floating gates
A memory cell transistor includes a high dielectric constant tunnel insulator, a metal floating gate, and a high dielectric constant inter-gate insulator comprising a metal oxide formed over a...
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7268030 |
Methods of forming semiconductor constructions
Thin film transistor based three-dimensional CMOS inverters utilizing a common gate bridged between a PFET device and an NFET device. One or both of the NFET and PFET devices can have an active...
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7268023 |
Method of forming a pseudo SOI substrate and semiconductor devices
The present invention is generally directed to a method of forming a pseudo SOI substrate and semiconductor devices. In one illustrative embodiment, the method comprises forming a plurality of...
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7268022 |
Stable PD-SOI devices and methods
One aspect of the present subject matter relates to a partially depleted silicon-on-insulator structure. The structure includes a well region formed above an oxide insulation layer. In various...
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7268018 |
Method for fabricating semiconductor component with stiffener and circuit decal
A semiconductor component includes a stiffener, a circuit decal attached to the stiffener, and a semiconductor die attached to the stiffener. The circuit decal includes conductors which function as...
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7268013 |
Method of fabricating a semiconductor die package having improved inductance characteristics
A ball grid array (BGA) package that includes a central cavity for receiving a semiconductor die therein is disclosed. The die rests on a base laminate, the die side of which includes traces...
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7268012 |
Methods for fabrication of thin semiconductor assemblies including redistribution layers and packages and assemblies formed thereby
Methods for creating redistribution layers for only selected dice, such as known good dice, to form relatively thin semiconductor component assemblies and packages, and the assemblies and packages...
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7268004 |
Thermoelectric control for field emission display
An active matrix display that does not require a transistor or similar current switching device at each pixel. Instead, the display employs in each pixel a temperature-controlled current source...
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7267999 |
MRAM layer having domain wall traps
A common pinned layer is shared by multiple memory cells in an MRAM device. The common pinned layer includes a plurality of domain wall traps that prevent the formation of domain walls within a...
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7267608 |
Method and apparatus for conditioning a chemical-mechanical polishing pad
A conditioner including abrasive elements for conditioning a polishing pad to be used in abrasive semiconductor substrate treatment processes, such as chemical-mechanical polishing or...
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7266879 |
Method for magnetically establishing an electrical connection with a contact of a semiconductor device component
A method for establishing electrical contact includes nonrigidly applying force to a semiconductor substrate in directions substantially normal to a plane of the semiconductor substrate includes a...
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7266633 |
System and method for communicating the synchronization status of memory modules during initialization of the memory modules
A memory system includes a memory hub controller coupled to a plurality of memory modules each of which includes a memory hub. The memory hub controller and the memory hubs each include at least...
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7265706 |
Minimized SAR-type column-wide ADC for image sensors
An improved analog-to-digital converter wherein a minimal amount of circuitry is provided for conversion of an analog signal to a series of digital bits. A comparator is provided for generating...
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7265674 |
Thin flexible, RFID labels, and method and apparatus for use
A radio frequency identification (REID) device may include a first, thin, flexible sheet, an antenna, and an integrated circuit. A surface portion of the first sheet may be affixed to a second,...
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7265563 |
Test method for semiconductor components using anisotropic conductive polymer contact system
A contact system for electrically engaging semiconductor components includes an interface board mountable to an automated test handler, and a floating substrate on the interface board. The...
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7265529 |
Zero power start-up circuit
An improved start-up circuit and method for self-bias circuits is described that applies a start-up voltage and current to a self-bias circuit to initialize its operation in its desired stable...
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7265453 |
Semiconductor component having dummy segments with trapped corner air
A semiconductor component includes a leadframe, a die, upper and lower body segments encapsulating the die, and dummy segments on the leadframe. The dummy segments are configured to vent trapped...
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7265414 |
NROM memory device with a high-permittivity gate dielectric formed by the low temperature oxidation of metals
A high permittivity gate dielectric formed by low temperature metal oxidation is used in an NROM memory cell. The gate dielectric has a dielectric constant greater than silicon dioxide and is...
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7265330 |
Microelectronic imagers with optical devices and methods of manufacturing such microelectronic imagers
Microelectronic imager assemblies comprising a workpiece including a substrate and a plurality of imaging dies on and/or in the substrate. The substrate includes a front side and a back side, and...
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7265328 |
Method and apparatus providing an optical guide for an imager pixel having a ring of air-filled spaced slots around a photosensor
A device and method to provide an optical guide of a pixel to guide incoming light onto a photosensor of the pixel and to improve the optical crosstalk immunity of an image sensor. The optical...
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7265052 |
Methods of forming conductive through-wafer vias
The present invention is generally directed to various methods of forming conductive through-wafer vias. In one illustrative embodiment, the method comprises providing a layer of semiconducting...
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7265016 |
Stepped gate configuration for non-volatile memory
A memory device having a field effect transistor with a stepped gate dielectric and a method of making the same are herein disclosed. The stepped gate dielectric is formed on a semiconductor...
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7265012 |
Formation of standard voltage threshold and low voltage threshold MOSFET devices
Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked,...
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7264988 |
Electro-and electroless plating of metal in the manufacture of PCRAM devices
Non-volatile, resistance variable memory devices, integrated circuit elements, and methods of forming such devices are provided. According to one embodiment of a method of the invention, a memory...
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7264844 |
Forming oxide buffer layer for improved magnetic tunnel junctions
A metal manganese oxide buffer layer is used to seed a barrier layer in a magnetic tunnel junction memory element having pinned and free magnetic layers. An alumina tunnel barrier layer is formed...
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7264768 |
Single substrate annealing of magnetoresistive structure
A device for magnetically annealing magnetoresistive elements formed on wafers includes a heated chuck and a delivery mechanism for individually placing the wafers individually on the chuck one at...
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7264742 |
Method of planarizing a surface
A method for removing at least a portion of a structure, such as a layer, film, or deposit, including ruthenium metal and/or ruthenium dioxide includes contacting the structure with a material...
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7264539 |
Systems and methods for removing microfeature workpiece surface defects
Systems and methods for removing microfeature workpiece surface defects are disclosed. A method for processing a microfeature workpiece in accordance with one embodiment includes removing surface...
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7264456 |
Leadframe and method for reducing mold compound adhesion problems
An integrated circuit leadframe has a pair of leadframe rails that are specially treated to adhere to injection mold compounds to a lesser or greater degree than portions of the leadframe rails...
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7263768 |
Method of making a semiconductor device having an opening in a solder mask
The present invention features a novel design for a fiducial and pin one indicator that utilizes a single solder resist opening in a die mounting substrate to perform the combined functions of...
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7263570 |
Method of providing an interface to a plurality of peripheral devices using bus adapter chips
A method of electrically coupling a central processing unit (CPU) of a network server to a plurality of network interface modules. The method comprises providing each of the plurality of network...
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7263543 |
Method for manipulating data in a group of processing elements to transpose the data using a memory stack
A method for transposing data in a plurality of processing elements is comprised of a plurality of shifting operations and a plurality of storing operations. The shifting and storing operations are...
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7263022 |
No-precharge FAMOS cell and latch circuit in a memory device
The fuse and latch circuit has a Floating gate Avalanche injection Metal Oxide Semiconductor (FAMOS) transistor (fuse) that is coupled to a read circuit. The read circuit includes circuitry that...
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7263017 |
AC sensing for a resistive memory
Alternating current is used to sense a logic state of a memory cell that has a resistive memory element. The memory element can be in an array and a memory device can include the array and...
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7263006 |
Memory block erasing in a flash memory device
The flash memory cell erase operation performs an erase operation at a first erase voltage for a first erase time. An erase verify read operation is then performed for an increasing sensing time...
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7262996 |
Programmable soft-start control for charge pump
A programmable soft-start control circuit having two memory registers for regulating the ramp-up time period of charging current in a charge pump of an integrated circuit. The two memory registers...
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7262780 |
Simple and robust color saturation adjustment for digital images
A method and system for adjusting saturation in digital images that operates as closely as possible to the long-, medium-, short-(LMS) cone spectral response space. According to the method, a...
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7262641 |
Current differential buffer
The present technique relates to a method and apparatus for operating a differential buffer. In the differential buffer, a first stage may include a differential pair configured to receive input...
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