Matches 751 - 800 out of 17288 < 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 >
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7326960 Semiconductor circuit constructions  
The invention includes a method of forming semiconductor circuitry wherein a first semiconductor structure comprising a first monocrystalline semiconductor substrate is bonded to a second...
7326950 Memory device with switching glass layer  
A memory device, such as a PCRAM, including a chalcogenide glass backbone material with germanium telluride glass and methods of forming such a memory device.
7326904 In-pixel kTC noise suppression using circuit techniques  
A circuit and method for reducing kTC noise in CMOS imagers while minimizing power dissipation is disclosed. Correlated double sampling (CDS) is performed within each pixel such that the reset...
7326647 Dry etching process to form a conductive layer within an opening without use of a mask during the formation of a semiconductor device  
A method for use in fabrication of a semiconductor device comprises forming a conformal conductive layer over a planarized surface of a dielectric layer, and within an opening formed in the...
7326611 DRAM arrays, vertical transistor structures and methods of forming transistor structures and DRAM arrays  
The invention includes a method of forming a semiconductor construction. Dopant is implanted into the upper surface of a monocrystalline silicon substrate. The substrate is etched to form a...
7326607 Imager floating diffusion region and process for forming same  
The present invention provides an imager device with a floating diffusion region resistant to charge leakage. The floating diffusion region is formed having a first doped region and a second doped...
7326606 Semiconductor processing methods  
In one aspect, the invention provides a method of forming a contact opening to a conductive line. In one preferred implementation, a contact opening is formed to a conductive line which overlies a...
7326597 Gettering using voids formed by surface transformation  
One aspect of this disclosure relates to a method for creating a gettering site in a semiconductor wafer. In various embodiments, a predetermined arrangement of a plurality of holes is formed in...
7326591 Interconnecting substrates for microelectronic dies, methods for forming vias in such substrates, and methods for packaging microelectronic devices  
Substrates for mounting microelectronic dies, methods for forming vias in such substrates, and methods for packaging microelectronic devices are disclosed herein. A method of manufacturing a...
7326503 Process for color filter array residual pigment removal  
A method of fabricating a color filter array including the removal of unwanted residual color pigments. A substrate is coated with a colored photoresist layer. The photoresist layer is patterned....
7326316 Electrical interconnect using locally conductive adhesive  
An anisotropic electrically conducting interconnect is disclosed in which an adhesive comprising particles having a breakable coating of at feast one electrically nonconductive material is...
7326105 Retaining rings, and associated planarizing apparatuses, and related methods for planarizing micro-device workpieces  
Retaining rings and associated planarizing apparatuses, and related methods for planarizing micro-device workpieces are disclosed herein. A carrier head configured in accordance with one embodiment...
7326066 Adapter for non-permanently connecting integrated circuit devices to multi-chip modules and method of using same  
An adapter and method for aligning and connecting the external leads of at least one integrated circuit device to conductors on a substrate of a multi-chip module. The adapter includes a component...
7325089 Controller for refreshing memories  
A memory utilizes a data refresh algorithm to preserve data integrity over disturbances caused by memory programming or erase operations. The memory device maintains a counter for each memory block...
7324690 Metal mask for light intensity determination and ADC calibration  
An apparatus and method for controlling gain characteristics in a CMOS imager and for calibrating light intensity and analog to digital conversion in a pixel array. A mask with varying sized...
7324401 Memory device and method having programmable address configurations  
A memory device includes a configurable address register having a first set of input buffers coupled to a first set on address bus terminals and a second set of input buffers coupled to a second...
7324400 Programming and evaluating through PMOS injection  
A PMOS transistor includes a gate, drain, and source in a substrate and is isolated from adjacent transistors in the substrate by shallow trench isolation. The transistor is programmed by applying...
7324383 Selective slow programming convergence in a flash memory device  
A plurality of memory cells are programmed with incrementally increased programming pulses applied to word lines to which the memory cells are coupled. After each pulse, a verify operation...
7324381 Low power multiple bit sense amplifier  
A sense amplifier for multiple level flash memory cells is comprised of a voltage ramp generator that generates a ramp voltage signal. Reference sense amplifiers compare an input reference current...
7324367 Memory cell and method for forming the same  
A semiconductor memory cell structure having 4 F 2 dimensions and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed in the...
7324290 Variable focus optic module and optic system  
A variable focus optic module is provided with a housing, a lens assembly, and a protrusion and recess system. The lens assembly is movably disposed in operable relationship with the housing. The...
7323896 Device and method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer  
A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited...
7323772 Ball grid array structures and tape-based method of manufacturing same  
Semiconductor device packages formed in accordance with methods of packaging semiconductor dice in grid array-type semiconductor device packages using conventional lead frame or lead lock tape...
7323767 Standoffs for centralizing internals in packaging process  
A semiconductor device, semiconductor die package, mold tooling, and methods of fabricating the device and packages are provided. In one embodiment, the semiconductor device comprises a pair of...
7323756 Method of composite gate formation  
Methods for forming a nitride barrier film layer in semiconductor devices such as gate structures, and barrier layers, semiconductor devices and gate electrodes are provided. The nitride layer is...
7323755 Method of composite gate formation  
Methods for forming a nitride barrier film layer in semiconductor devices such as gate structures, and barrier layers, semiconductor devices and gate electrodes are provided. The nitride layer is...
7323739 Semiconductor device having recess and planarized layers  
A method for forming a floating gate semiconductor device such as an electrically erasable programmable read only memory is provided. The device includes a silicon substrate having an electrically...
7323738 MIS capacitor and method of formation  
An MIS capacitor with low leakage and high capacitance is disclosed. A layer of hemispherical grained polysilicon (HSG) is formed as a lower electrode. Prior to the dielectric formation, the...
7323737 DRAM constructions and electronic systems  
The invention includes methods in which metal oxide dielectric materials are deposited over barrier layers. The barrier layers can comprise compositions of metal and one or more of carbon, boron...
7323424 Semiconductor constructions comprising cerium oxide and titanium oxide  
The invention includes semiconductor constructions comprising dielectric materials which contain cerium oxide and titanium oxide. The dielectric materials can contain a homogeneous distribution of...
7323412 Atomic layer deposition methods, and methods of forming materials over semiconductor substrates  
The invention includes methods in which at least two different precursors are flowed into a reaction chamber at different and substantially non-overlapping times relative to one another to form a...
7323400 Plasma processing, deposition and ALD methods  
A plasma processing method includes providing a substrate in a processing chamber, the substrate having a surface, and generating a plasma in the processing chamber. The plasma provides at least...
7323380 Single transistor vertical memory gain cell  
A high density vertical single transistor gain cell is realized for DRAM operation. The gain cell includes a vertical transistor having a source region, a drain region, and a floating body region...
7323353 Resonator for thermo optic device  
A resonator for thermo optic devices is formed in the same process steps as a waveguide and is formed in a depression of a lower cladding while the waveguide is formed on a surface of the lower...
7323292 Process for using photo-definable layers in the manufacture of semiconductor devices and resulting structures of same  
A process and related structure are disclosed for using photo-definable layers that may be selectively converted to insulative materials in the manufacture of semiconductor devices, including for...
7323231 Apparatus and methods for plasma vapor deposition processes  
One aspect of the invention is directed toward a method of forming a conductive layer on a microfeature workpiece. In one embodiment, the method comprises placing a microfeature workpiece in a...
7323064 Supercritical fluid technology for cleaning processing chambers and systems  
The invention includes a method of cleaning a processing chamber by introducing supercritical fluid into the processing chamber. A residue over an internal chamber surface is contacted with the...
7322511 Apparatus and method for printing micro metal structures  
A method and device for printing liquid material such as liquid solder is provided. C4 structures as small as 10 microns in diameter can be produced using devices and methods described above....
7322002 Erasure pointer error correction  
Improved memory devices, circuitry, and data methods are described that facilitate the detection and correction of data in memory systems or devices in combination with a stored record of known...
7321951 Method for testing flash memory power loss recovery  
Non-volatile memory device, driver, and method is described that utilizes write or erase cycle tracking to interrupt or stop a non-volatile memory programming or erase operation at a selected point...
7321504 Static random access memory cell  
A static random access memory (SRAM) cell having an inverter and a tri-state inverter. An input of the inverter is coupled to an output of the tri-state inverter and an output of the inverter is...
7321455 Microelectronic devices and methods for packaging microelectronic devices  
Microelectronic devices and methods of packaging microelectronic devices are disclosed herein. In one embodiment, a method includes placing a plurality of singulated radiation responsive dies on a...
7321160 Multi-part lead frame  
A multi-part lead frame semiconductor device assembly is disclosed including a die bonded to a die paddle. A second lead frame including leads is superimposed and bonded onto the first lead frame....
7321150 Semiconductor device precursor structures to a double-sided capacitor or a contact  
A method of forming a double-sided capacitor using at least one sacrificial structure, such as a sacrificial liner or a sacrificial plug. A sacrificial liner is formed along sidewalls of at least...
7321149 Capacitor structures, and DRAM arrays  
A patterned mask can be formed as follows. A first patterned photoresist is formed over a masking layer and utilized during a first etch into the masking layer. The first etch extends to a depth in...
7321148 Capacitor constructions and rugged silicon-containing surfaces  
The invention encompasses a method of forming a rugged silicon-containing surface. A layer comprising amorphous silicon is provided within a reaction chamber at a first temperature. The temperature...
7320933 Double bumping of flexible substrate for first and second level interconnects  
An apparatus and method for improving the yield and reducing the cost of forming a semiconductor device assembly. An interposer substrate is formed with interconnections in the form of conductive...
7320911 Methods of forming pluralities of capacitors  
A method of forming a plurality of capacitors includes providing a plurality of capacitor electrodes comprising sidewalls. The plurality of capacitor electrodes are supported at least in part with...
7320049 Detection circuit for mixed asynchronous and synchronous memory operation  
A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device The memory access mode detection circuit receives the memory address signals,...
7319935 System and method for analyzing electrical failure data  
A system and method to perform analysis on test results of multiple integrated circuits. Based on the analysis, the system and method display a wafer map having map indicators representing...
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