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7531421 |
Semiconductor capacitor structure and method to form same
A semiconductor capacitor structure comprising sidewalls of conductive hemispherical grained material, a base of metal silicide material, and a metal nitride material overlying the conductive...
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7531395 |
Methods of forming a layer comprising epitaxial silicon, and methods of forming field effect transistors
Methods of forming layers comprising epitaxial silicon, and methods of forming field effect transistors are disclosed. A method of forming a layer comprising epitaxial silicon includes etching an...
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7531379 |
Method of forming CMOS imager with capacitor structures
A charge storage capacitor which is connected to various light sensitive and/or electrical elements of a CMOS imager, as well as methods of formation, are disclosed. The charge storage capacitor...
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7531373 |
Methods of forming a conductive interconnect in a pixel of an imager and in other integrated circuitry
A method of forming conductive interconnects includes forming a node of a circuit component on a substrate. A conductive metal line is formed at a first metal routing level that is elevationally...
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7530877 |
Semiconductor processor systems, a system configured to provide a semiconductor workpiece process fluid
Semiconductor processor systems, systems configured to provide a semiconductor workpiece process fluid, semiconductor workpiece processing methods, methods of preparing semiconductor workpiece...
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7529969 |
Memory device internal parameter reliability
Embodiments herein may store redundant copies of an operational parameter associated with an internal operation of a memory device. The redundant copies and associated parity bits may be stored in...
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7529951 |
Memory subsystem voltage control and method that reprograms a preferred operating voltage
A method and apparatus for providing a preferred operating voltage to a memory device as specified by a stored configuration parameter. The apparatus includes a nonvolatile memory configured to...
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7529896 |
Memory modules having a memory hub containing a posted write buffer, a memory device interface and a link interface, and method of posting write requests in memory modules
A memory module includes a memory hub coupled to several memory devices. The memory hub includes a posted write buffer that stores write requests so that subsequently issued read requests can first...
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7529882 |
Dynamic volume management for flash memories
A method for managing a range of memory in a flash memory space in which a plurality of data objects are stored. A volume defined for the range of memory has a first end and second end, with a...
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7529460 |
Zinc oxide optical waveguides
The present disclosure includes methods, devices, and systems having zinc oxide waveguides for optical signal interconnections. One optical signal interconnect system includes an oxide layer on a...
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7529318 |
Circuit and method for reducing noise interference in digital differential input receivers
A circuit and method reduces noise signals coupled to a reference voltage used by a digital differential input receiver having an input that is coupled to an input/output terminal. The circuit and...
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7529129 |
Single level cell programming in a multiple level cell non-volatile memory device
A multiple level cell memory array has an area that can be programmed as single level cells. The cells to be programmed are initially programmed with the desire data into either the least...
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7528877 |
Method and system for reducing mismatch between reference and intensity paths in analog to digital converters in CMOS active pixel sensors
A circuit for reducing a mismatch between a reference path to which a reference voltage is applied and an intensity path to which an intensity voltage is applied from an active pixel sensor...
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7528638 |
Clock signal distribution with reduced parasitic loading effects
Clock signal distribution systems with reduced parasitic loading effects are provided. A reference clock is frequency-divided to produce a lower frequency clock signal. A delay-locked loop (DLL)...
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7528624 |
Output buffer and method having a supply voltage insensitive slew rate
An output buffer includes a final driver formed by first and second MOSFET transistors that alternately couple an output terminal to respective supply voltages. The output terminal is biased to a...
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7528536 |
Protective layer for corrosion prevention during lithography and etch
Forming a protective layer such as chromium, chrome alloys, nickel or cobalt as a cap over an aluminum film protects an underlying ITO layer from corrosion during the fabrication of flat panel...
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7528491 |
Semiconductor components and assemblies including vias of varying lateral dimensions
Methods for forming vias are disclosed. The methods include providing a substrate having a first surface and an opposing, second surface. A first opening, a second opening, and a third opening are...
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7528477 |
Castellation wafer level packaging of integrated circuit chips
Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and,...
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7528463 |
Semiconductor on insulator structure
An apparatus and a method for forming the apparatus include a semiconductor layer on an insulating substrate, where the substrate is a different material than the semiconductor layer, and has a...
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7528440 |
Vertical gain cell
A vertical cell is realized. The cell includes a first vertical metal oxide semiconductor (MOS) transistor having a body between a drain region and a source region and a second vertical MOS...
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7528439 |
Vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array
A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by a process in which source, drain and...
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7528435 |
Semiconductor constructions
The invention encompasses methods of forming metal nitride proximate dielectric materials. The metal nitride comprises two portions, with one of the portions being nearer the dielectric material...
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7528430 |
Electronic systems
The invention includes a method of forming a rugged semiconductor-containing surface. A first semiconductor layer is formed over a substrate, and a second semiconductor layer is formed over the...
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7528424 |
Integrated circuitry
This invention includes methods of forming layers comprising epitaxial silicon, and field effect transistors. In one implementation, a method of forming a layer comprising epitaxial silicon...
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7528401 |
Agglomeration elimination for metal sputter deposition of chalcogenides
A method for fabricating chalcogenide materials on substrates, which reduces and/or eliminates agglomeration of materials on the chalcogenide materials; and system and devices for performing the...
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7528064 |
Interconnect structures with bond-pads and methods of forming bump sites on bond-pads
Microelectronic workpieces that have bump sites over bond-pads and methods of fabricating such bump sites. One embodiment of such a workpiece, for example, includes a substrate having a plurality...
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7528043 |
Scalable gate and storage dielectric
Gate and storage dielectric systems and methods of their fabrication are presented. A passivated overlayer deposited between a layer of dielectric material and a gate or first storage plate...
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7528037 |
Flash memory having a high-permittivity tunnel dielectric
A high permittivity tunneling dielectric is used in a flash memory cell to provide greater tunneling current into the floating gate with smaller gate voltages. The flash memory cell has a substrate...
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7528007 |
Methods for assembling semiconductor devices and interposers
A method for assembling one or more semiconductor devices with an interposer includes positioning the one or more semiconductor devices within a receptacle that extends through the interposer, on a...
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7527693 |
Apparatus for improved delivery of metastable species
The invention includes a deposition system having a reservoir for containment of a metastable specie connected to a deposition chamber. The system includes a metastable specie generating catalyst...
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7527545 |
Methods and tools for controlling the removal of material from microfeature workpieces
Methods and apparatus for controlling the removal of material from microfeature workpieces in abrasive removal processes. An embodiment of such a method comprises irradiating a periodic structure...
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7526713 |
Low power cost-effective ECC memory system and method
A memory controller couples 32-bit data words to and from a DRAM. The DRAM generates error checking and correcting syndromes to check and correct read data. The DRAM generates the syndromes from...
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7526709 |
Error detection and correction in a CAM
An error detection and correction circuit is connected to at least one memory bank of a CAM device. During background processing (i.e., when the CAM is not performing reading, writing or searching...
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7526704 |
Testing system and method allowing adjustment of signal transmit timing
A test system includes respective clock domain crossing circuits coupling memory device signals to a memory device being tested. The clock domain crossing circuit includes a ring buffer into which...
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7525842 |
Increased NAND flash memory read throughput
A method of reading sequential pages of flash memory from alternating memory blocks comprises loading data from a first page into a first primary data cache and a second page into a second primary...
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7525841 |
Programming method for NAND flash
A NAND architecture non-volatile memory device and programming process is described that programs the various cells of strings of non-volatile memory cells utilizing a drain-side self boost,...
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7525458 |
Method and apparatus for converting parallel data to serial data in high speed applications
A method and apparatus to convert parallel data to serial data is provided. More specifically, there is provided a parallel-to-serial converter comprising a data pipeline configured to receive...
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7525379 |
Low voltage CMOS differential amplifier
There is provided a device including a PMOS differential amplifier and an NMOS differential amplifier. The NMOS differential amplifier is coupled to the PMOS differential amplifier. The device is...
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7525354 |
Local coarse delay units
Methods, circuits, devices, and systems are provided, including embodiments with local coarse delay units. One embodiment includes generating a first delayed signal, a second delayed signal, and a...
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7525352 |
Current differential buffer
A memory device having a differential buffer is disclosed. In some embodiments, the memory device includes a differential buffer having a differential pair that is configured to receive input...
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7525332 |
On-chip substrate regulator test mode
An on-chip circuit for defect testing with the ability to maintain a substrate voltage at a level more positive or more negative than a normal negative operating voltage level of the substrate....
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7525164 |
Strained Si/SiGe/SOI islands and processes of making same
A process of making a strained silicon-on-insulator structure is disclosed. A recess is formed in a substrate to laterally isolate an active area. An undercutting etch forms a bubble recess under...
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7525149 |
Combined volatile and non-volatile memory device with graded composition insulator stack
A memory device is fabricated with a graded composition tunnel insulator layer. This layer is formed over a substrate with a drain and a source region. The tunnel insulator is comprised of a graded...
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7525141 |
Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines
A memory array with data/bit lines extending generally in a first direction formed in an upper surface of a substrate and access transistors extending generally upward and aligned generally atop a...
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7525134 |
CMOS imager pixel designs
A charge storage capacitor which is connected to various light sensitive and/or electrical elements of a CMOS imager, as well as methods of formation, are disclosed. The charge storage capacitor...
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7524756 |
Process of forming a semiconductor assembly having a contact structure and contact liner
A contact structure and a method of forming thereof for semiconductor devices or assemblies are described. The method provides process steps to create a contact structure encompassed by a...
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7524410 |
Methods and apparatus for removing conductive material from a microelectronic substrate
A method and apparatus for removing conductive material from a microelectronic substrate is disclosed. One method includes disposing an electrolytic liquid between a conductive material of a...
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7523400 |
Text based markup language resource interface
A software control method and apparatus for displaying a text based markup language interface. The interface can interact with a computer to provide reference documents, install system drivers and...
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7523381 |
Non-volatile memory with error detection
Data move operations in a memory device are described that enable identification of data errors. Error detection circuitry in the memory device can be operated using parity data or ECC data stored...
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7522466 |
DRAM power bus control
A dynamic random access memory (DRAM) is provided that has separate array and peripheral power busing to isolate array noise from peripheral circuits such as delay lock loops during row activations...
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