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7404162 Buffering technique using structured delay skewing  
A line buffering technique in which a plurality of line buffers are arranged based on a determined average number of branches and stages that are necessary to implement the buffers based on design...
7404124 On-chip sampling circuit and method  
Through addressing circuitry, a sampling circuit can choose a unique internal node/signal on an encapsulated/packaged chip to be output to one or more drivers. The chosen signals available at the...
7404071 Memory modules having accurate operating current values stored thereon and methods for fabricating and implementing such devices  
Memory modules having accurate operating current values stored thereon and methods for fabricating and implementing such devices to improve system performance. Memory modules comprising a number of...
7404066 Active memory command engine and method  
A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU commands to a processing array...
7404033 Method for reading while writing to a single partition flash memory  
A device manager receives an operation request for a memory device. The device manager suspends interrupts to be serviced and determines if there is sufficient time available to perform the...
7403444 Selectable memory word line deactivation  
Circuitry and methods allow selected memory word lines (WLs) to be deactivated without using a global deactivate signal. All active WLs do not therefore have to be deactivated simultaneously, which...
7403425 Programming a flash memory device  
An initial verify read operation is performed after each programming pulse. The verify voltage starts at an initial verify voltage for the first word line and increases for each word line that is...
7403423 Sensing scheme for low-voltage flash memory  
Single-ended sensing devices for sensing a programmed state of a non-volatile memory cell are adapted for use in low-voltage memory devices. Methods of their operation include precharging an input...
7403419 Integrated DRAM-NVRAM multi-level memory  
An integrated DRAM-NVRAM, multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate floating plate device. The floating plate device provides enhanced charge...
7403416 Integrated DRAM-NVRAM multi-level memory  
An integrated DRAM-NVRAM, multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate floating plate device. The floating plate device provides enhanced charge...
7403060 Forward biasing protection circuit  
A forward biasing protection circuit is provided. More specifically, there is provided a device comprising a transistor, a resistive element coupled to the body terminal of the transistor, and a...
7403044 Method of producing balanced data output  
Strobe signals are coupled to a phase detector which compares rising and falling edges of the respective strobe signals. If the phase detector determines that there is a mismatch, it outputs an UP...
7403033 MOS linear region impedance curvature correction  
A system and method to correct or cancel MOS linear region impedance curvature employing an analog solution to trim out the MOS linear region impedance curvature while accommodating PVT spreads in...
7402908 Intermediate semiconductor device structures  
A method of forming a metal pattern on a dielectric layer that comprises forming at least one trench in a dielectric layer formed from a photosensitive, insulative material. A conformed metal layer...
7402902 Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice  
An inventive electronic device, such as a multi-chip module (MCM), a Single In-line Memory Module (SIMM), or a Dual In-line Memory Module (DIMM), includes a base, such as a printed circuit board,...
7402879 Layered magnetic structures having improved surface planarity for bit material deposition  
The present invention provides a method of fabricating a portion of a memory cell, the method comprising providing a first conductor in a trench which is provided in an insulating layer and...
7402876 Zr— Sn—Ti—O films  
A dielectric film containing Zr—Sn—Ti—O formed by atomic layer deposition using a TiI 4 precursor and a method of fabricating such a dielectric film produce a reliable dielectric layer...
7402861 Memory cells and select gates of NAND memory arrays  
A select gate of a NAND memory array has a first dielectric layer formed on a semiconductor substrate. A first conductive layer is formed on the first dielectric layer. Conductive spacers are...
7402850 Back-side trapped non-volatile memory device  
Non-volatile memory devices and arrays are described that utilize back-side trapped floating node memory cells with band-gap engineered gate stacks with asymmetric tunnel barriers. Embodiments of...
7402833 Multilayer dielectric tunnel barrier used in magnetic tunnel junction devices, and its method of fabrication  
A multilayer dielectric tunnel barrier structure and a method for its formation which may be used in non-volatile magnetic memory elements comprises an ALD deposited first nitride junction layer...
7402789 Methods for pixel binning in an image sensor  
Embodiments provide structures and methods for binning pixel signals of a pixel array. Pixel signals for pixels in an element of the array are binned simultaneously. Pixels in an element are...
7402533 Masking without photolithography during the formation of a semiconductor device  
A method for forming a semiconductor device comprises forming a dielectric layer over a semiconductor wafer substrate assembly having closely spaced regions, such as a memory transistor array, and...
7402526 Plasma processing, deposition, and ALD methods  
A plasma processing method includes providing a substrate in a processing chamber, the substrate having a surface, and generating a plasma in the processing chamber. The plasma provides at least...
7402518 Atomic layer deposition methods  
A first precursor gas is flowed to the substrate within the chamber effective to form a first monolayer on the substrate. A second precursor gas different in composition from the first precursor...
7402516 Method for making integrated circuits  
Integrated circuits, the key components in thousands of electronic and computer products, include interconnected networks of electrical components. The components are typically wired, or...
7402512 High aspect ratio contact structure with reduced silicon consumption  
A high aspect ratio contact structure formed over a junction region in a silicon substrate comprises a titanium interspersed with titanium silicide layer that is deposited in the contact opening...
7402498 Methods of forming trench isolation regions  
The invention includes methods of forming trench isolation regions. In one implementation, a masking material is formed over a semiconductor substrate. The masking material comprises at least one...
7402489 Capacitor compatible with high dielectric constant materials having a low contact resistance layer and the method for forming same  
A storage cell capacitor and a method for forming the storage cell capacitor having a storage node electrode including a barrier layer interposed between a conductive plug and an oxidation...
7402453 Microelectronic imaging units and methods of manufacturing microelectronic imaging units  
Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one embodiment, a method includes coupling a...
7402451 Optimized transistor for imager device  
An imager device that has mitigated dark current leakage and punch-through protection. The transistor associated with the photoconversion device is formed with a single (i.e, one-sided) active area...
7402379 Resist exposure system and method of forming a pattern on a resist  
A resist exposure system and a method of forming a pattern on a resist are provided and include an exposure source, a photoresist composition, and a mask positioned therebetween. The resist...
7402259 Chemical-mechanical polishing methods  
A chemical-mechanical polishing (CMP) method includes applying a solid abrasive material to a substrate, polishing the substrate, flocculating at least a portion of the abrasive material, and...
7402094 Fixed-abrasive chemical-mechanical planarization of titanium nitride  
Planarizing solutions, and their methods of use, for removing titanium nitride from the surface of a substrate using a fixed-abrasive planarizing pad. The planarizing solutions take the form of an...
7401267 Program failure recovery  
Methods and apparatus are provided. A method of operating a memory device includes detecting a programming failure at a first location of a memory array, preserving data within the memory device...
7401010 Methods of forming radiation-patterning tools; carrier waves and computer readable media  
The invention includes a method for placement of sidelobe inhibitors on a radiation-patterning tool. Elements of the tool are represented by design features in a modeling domain. The modeling...
7400549 Memory block reallocation in a flash memory device  
A non-volatile memory device has the pages of a certain memory block reallocated to other blocks in order to increase decrease disturb and increase reliability. Each of the reallocation blocks that...
7400544 Actively driven VREF for input buffer noise immunity  
A memory device including a circuit for actively driving a reference voltage in a memory device is disclosed. A circuit integrated in a memory device and coupled to an external voltage source...
7400539 Memory device having terminals for transferring multiple types of data  
A device includes a number of terminals for transferring input data and output data to and from a memory array. The memory device includes an auxiliary circuit for receiving input auxiliary...
7400533 Mimicking program verify drain resistance in a memory device  
A selected word line is biased with a program verify voltage. A predetermined quantity of unselected word lines that are between the selected word line and the bit line are biased with a modified V...
7400532 Programming method to reduce gate coupling interference for non-volatile memory  
A non-volatile memory device and programming process is described that compensates for coupling effects on threshold gate voltages of adjacent floating gate or non-conductive floating node memory...
7400389 Method and apparatus for testing image sensors  
Methods and apparatuses for testing image sensors are disclosed. Desirable apparatuses of the present invention include image sensor testing devices comprising a digital light projection system...
7400350 System and method for collecting images of a monitored device  
A system and method for collecting images of monitored devices, such as utility meters for electricity, gas and water, captures a digital image of a monitored device and produces a difference...
7400124 Apparatus and methods for regulated voltage  
An electronic system according to various aspects of the present invention includes a memory and a supply regulation circuit having a regulated output to provide a selected voltage level. In one...
7400043 Semiconductor constructions  
The invention includes a method of forming a metal-containing film over a surface of a semiconductor substrate. The surface is exposed to a supercritical fluid. The supercritical fluid has H 2 , at...
7400032 Module assembly for stacked BGA packages  
Ball grid array packages that can be stacked to form highly dense components and the method for stacking ball grid arrays are disclosed. The ball grid array packages comprise flexible or rigid...
7400012 Scalable Flash/NV structures and devices with extended endurance  
Devices and methods are provided with respect to a gate stack for a nonvolatile structure. According to one aspect, a gate stack is provided. One embodiment of the gate stack includes a tunnel...
7400004 Isolation structures for preventing photons and carriers from reaching active areas and methods of formation  
Regions of an integrated circuit are isolated by a structure that includes at least one isolating trench on the periphery of an active area. The trench is deep, extending at least about 0.5 μm...
7399714 Method of forming a structure over a semiconductor substrate  
The invention includes a method of forming a structure over a semiconductor substrate. A silicon dioxide containing layer is formed across at least some of the substrate. Nitrogen is formed within...
7399671 Disposable pillars for contact formation  
Sacrificial plugs for forming contacts in integrated circuits, as well as methods of forming connections in integrated circuit arrays are disclosed. Various pattern transfer and etching steps can...
7399666 Atomic layer deposition of Zr3N4/ZrO2 films as gate dielectrics  
The use of atomic layer deposition (ALD) to form a dielectric layer of zirconium nitride (Zr 3 N 4 ) and zirconium oxide (ZrO 2 ) and a method of fabricating such a dielectric layer produces a...
Matches 1 - 50 out of 17197 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >