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US20150213161 OPTICAL MODEL EMPLOYING PHASE TRANSMISSION VALUES FOR SUB-RESOLUTION ASSIST FEATURES  
Optical simulation can be performed employing a calibrated printing model, in which a unique phase transmission value is assigned to each type of sub-resolution assist features (SRAFs). The...
US20140380255 PRINTING PROCESS CALIBRATION AND CORRECTION  
Various embodiments include approaches for calibrating a model for a lithographic printing process. Some embodiments include a computer-implemented method for calibrating a model for a...
US20150213188 CONCURRENT TIMING-DRIVEN TOPOLOGY CONSTRUCTION AND BUFFERING FOR VLSI ROUTING  
A system and method for topology construction for long and complex fan-out networks such as encountered in microprocessors include a modified Steiner tree algorithm with concurrent buffering to...
US20140149955 LOW-OVERHEAD MULTI-PATTERNING DESIGN RULE CHECK  
Roughly described, a system enables quick and accurate depiction to a user of multi-patterning layout violations so that they may be corrected manually and in real time, and without interfering...
US20130074024 LOW-OVERHEAD MULTI-PATTERNING DESIGN RULE CHECK  
Roughly described, a system enables quick and accurate depiction to a user of multi-patterning layout violations so that they may be corrected manually and in real time, and without interfering...
US20130239076 DESIGN METHOD, DESIGN APPARATUS, AND PROGRAM PRODUCT FOR INCREMENTAL DESIGN SPACE EXPLORATION  
A design apparatus generates an optimal design condition by design space exploration. The apparatus including a source code parsing (301) which parses source code and generates a parse tree, a...
US20150149972 METHOD, DESIGN APPARATUS, AND PROGRAM PRODUCT FOR INCREMENTAL DESIGN SPACE EXPLORATION  
A design apparatus generates an optimal design condition by design space exploration. The apparatus including a source code parsing (301) which parses source code and generates a parse tree, a...
US20130252350 SYSTEM AND METHOD FOR GENERATING CARE AREAS FOR DEFECT INSPECTION  
A method of generating care areas is disclosed. An artwork file of a layout of a product is provided and a cell tree of the layout is formed. The cell tree includes a plurality of cells of the...
US20140310665 SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR TRANSLATING A COMMON HARDWARE DATABASE INTO A LOGIC CODE MODEL  
A system, method, and computer program product are provided for translating a hardware design. In use, a hardware design is received that is a graph-based common representation of a hardware...
US20130246983 GATE CD CONTROL USING LOCAL DESIGN ON BOTH SIDES OF NEIGHBORING DUMMY GATE LEVEL FEATURES  
A method of forming an IC including MOS transistors includes using a gate mask to form a first active gate feature having a line width W1 over an active area and a neighboring dummy feature having...
US20120107729 GATE CD CONTROL USING LOCAL DESIGN ON BOTH SIDES OF NEIGHBORING DUMMY GATE LEVEL FEATURES  
A method of forming an IC including MOS transistors includes using a gate mask to form a first active gate feature having a line width W1 over an active area and a neighboring dummy feature having...
US20130091482 METHOD AND APPARATUS FOR DESIGN SPACE EXPLORATION ACCELERATION  
A method for accelerating design space exploration of a target device when a behavioral description of the target device is given, includes: parsing the behavioral description to build a...
US20120192133 LOGIC DESIGN VERIFICATION TECHNIQUES FOR LIVENESS CHECKING WITH RETIMING  
A technique for verification of a retimed logic design using liveness checking includes assigning a liveness gate to a liveness property for an original netlist and assigning a fairness gate to a...
US20150040088 HYBRID DESIGN RULE FOR DOUBLE PATTERNING  
Among other things, one or more systems and techniques for generating or implementing a hybrid design rule set are provide herein. A set of color design rules and a set of color agnostic design...
US20140173534 RESOLUTION ENHANCING TECHNOLOGY USING PHASE ASSIGNMENT BRIDGES  
In one embodiment, a spacing is determined for each edge of a number of features in a photolithographic design. The edges have at least a partially predictable layout. Based on the spacing and the...
US20110283246 Method and Apparatus for Merging EDA Coverage Logs of Coverage Data  
An electronic design automation technology merges coverage logs. The coverage logs are generated by verification of a hardware description language circuit design. The coverage logs are merged as...
US20100175040 METHODOLOGY OF PLACING PRINTING ASSIST FEATURE FOR RANDOM MASK LAYOUT  
Embodiments of the present invention provide a method of placing printing assist features in a mask layout. The method includes providing a design layout having one or more designed features;...
US20110022997 METHOD FOR CONJECTURING EFFECTIVE WIDTH AND EFFECTIVE LENGTH OF GATE  
A method for conjecturing the effective size, i.e. the effective width or effective length, of a gate is disclosed. First, a first design gate group including a first gate design width and a first...
US20110061037 Generating Net Routing Constraints For Place And Route  
A method of generating net routing constraints for nets of an IC design includes generating a file with hashes organized by nets. Each hash has attributes of a net, e.g. net name, length, fanout,...
US20120317529 Rapid Estimation of Temperature Rise in Wires Due to Joule Heating  
A mechanism is provided for rapid estimation of temperature rise in wires due to Joule heating. The mechanism provides fast and accurate estimation of temperature rise in wires due to self...
US20140089879 CHARACTERIZATION BASED BUFFERING AND SIZING FOR SYSTEM PERFORMANCE OPTIMIZATION  
A method for timing optimization of an integrated circuit design using a timing optimization system comprising loading an original delay value and an original gate configuration net-list for an...
US20140084374 CELL DESIGN  
One or more techniques or systems for designing a cell are provided. The cell generally includes one or more transistors, such as a pass gate transistor, a pull up transistor, or a pull down...
US20110016446 Method for the Construction of Flexible Printed Circuit Boards  
A description is given of a method for the computer-aided construction of flexible printed circuit boards that are arranged in a housing (10) of a device. The method provides a 3D model for...
US20150186589 SYSTEM FOR AND METHOD OF PLACING AND ROUTING CLOCK STATIONS USING VARIABLE DRIVE-STRENGTH CLOCK DRIVERS BUILT OUT OF A SMALLER SUBSET OF BASE CELLS FOR HYBRID TREE-MESH CLOCK DISTRIBUTION NETWORKS  
Clock stations in a hybrid tree-mesh clock distribution network are placed and routed using placement information embedded in instance names of the macrocells that form the clock-distribution...
US20140248768 Mask Assignment Optimization  
A method for optimizing mask assignment for multiple pattern processes includes, through a computing system, defining which of a number of vias to be formed between two metal layers are critical...
US20140075397 PITCH-AWARE MULTI-PATTERNING LITHOGRAPHY  
A method, system, and computer program product for improving printability of a design of an integrated circuit (IC) using pitch-aware coloring for multi-patterning lithography (MPL) are provided...
US20100325591 Generation and Placement Of Sub-Resolution Assist Features  
Sub-resolution assist features (SRAFs) are placed in a template form and in series adjacent to main features in a layout design. After each SRAF template is placed, a clean-up process is conducted...
US20120311513 METHOD AND SYSTEM FOR IMPLEMENTING TOP DOWN DESIGN AND VERIFICATION OF AN ELECTRONIC DESIGN  
Disclosed is a method and system for performing design and verification using stepwise refinement techniques, which can also include or be referred to as “top-down” design verification. With the...
US20130159943 MACHINE LEARNING APPROACH TO CORRECT LITHOGRAPHIC HOT-SPOTS  
A method, system, and computer program product for machine learning approach for detecting and correcting lithographic hot-spots in an integrated circuit (IC) design are provided in the...
US20120266120 GLITCH POWER REDUCTION  
A method comprises reducing power consumption of an electronic circuit, wherein the electronic circuit comprises at least one logic cone with at least one gate having a single output net, wherein...
US20130341720 IMPLEMENTING GATE WITHIN A GATE UTILIZING REPLACEMENT METAL GATE PROCESS  
A method and circuit for implementing field effect transistors (FETs) having a gate within a gate utilizing a replacement metal gate process (RMGP), and a design structure on which the subject...
US20130061199 Navigating Analytical Tools Using Layout Software  
A background process installs a system hook for message interception of integrated circuit chip layout display software. A call message is intercepted through the system hook, and current layout...
US20150234974 MULTIPLE PATTERNING DESIGN WITH REDUCED COMPLEXITY  
A three color map can be built based on an integrated circuit (IC) layout, each color representing an exposure in a multiple (here triple) patterning lithography process and can include any...
US20150220676 COLOR-INSENSITIVE RULES FOR ROUTING STRUCTURES  
Methodologies and an apparatus enabling a generation of color undeterminable polygons in IC designs are disclosed. Embodiments include: determining a plurality of first routes extending...
US20150067633 COLOR-INSENSITIVE RULES FOR ROUTING STRUCTURES  
Methodologies and an apparatus enabling a generation of color undeterminable polygons in IC designs are disclosed. Embodiments include: determining a plurality of first routes extending...
US20120317533 SYSTEM AND METHOD FOR DYNAMICALLY INJECTING ERRORS TO A USER DESIGN  
A method and system for dynamically injecting errors to a user design is disclosed. In one embodiment, the user design having internal states and parameters is run in a design verification system....
US20110185325 Navigating Analytical Tools Using Layout Software  
A background process is used to install at least one system hook for message interception of integrated circuit chip layout display software. A call message is intercepted through the system hook,...
US20140007035 Method and Apparatus to Perform Footprint-Based Optimization Simultaneously with Other Steps  
A method comprising placing elements in a layout, performing clock tree synthesis, and performing routing. The method further comprising, in parallel with one of the clock tree synthesis or the...
US20110191740 ZONE-BASED OPTIMIZATION FRAMEWORK  
Some embodiments of the present invention provide techniques and systems for efficiently optimizing a circuit design for one or more multi-mode multi-corner (MCMM) scenarios. A system can select...
US20110035713 CIRCUIT BOARD DESIGN SYSTEM AND METHOD  
A method and system for designing a circuit board designs wiring of the circuit board, and determines electronic rules and physical rules of the wiring design. The method and system creates a...
US20150169819 DESIGN RULE CHECKING FOR CONFINING WAVEFORM INDUCED CONSTRAINT VARIATION IN STATIC TIMING ANALYSIS  
A method for design rule checking (DRC) during static timing analysis (STA) of an integrated circuit (IC) design comprises analyzing cells with distorted waveforms in a cell library and generating...
US20120011478 MERGING SUB-RESOLUTION ASSIST FEATURES OF A PHOTOLITHOGRAPHIC MASK  
Merging sub-resolution assist features includes receiving a mask pattern that includes the sub-resolution assist features. A first sub-resolution assist feature is selected to merge with a second...
US20110258589 CLOCK DISTRIBUTION CIRCUIT AND LAYOUT DESIGN METHOD USING THE SAME  
A layout design method in accordance with an exemplary aspect of the present invention is a layout design method for a clock tree circuit, including disposing a first clock distribution circuit in...
US20130159954 DESIGN METHOD OF ON-BOARD WIRING  
A design method of on-board wiring for a designed circuit includes determining a severity as a crosstalk prevention index for a pair of wires based on a generated noise level of a damaging side...
US20140282317 ARRIVAL EDGE USAGE IN TIMING ANALYSIS  
A logic design is analyzed using static timing analysis and timing edge tracking for various nets within the logic design. Crosstalk analysis is performed on the logic design to evaluate timing...
US20130298093 Method of Predicting Contention Between Electronic Circuit Drivers  
Software method to identify presence of multiple digital drivers disposed in a manner that creates multiple conflicting current paths in complex electronic circuit designs. Digital drivers are...
US20120110528 METHOD OF PREDICTING ELECTRONIC CIRCUIT FLOATING GATES  
Software method to identify which transistor gates float, and why, in complex, multi-transistor, electronic circuit designs. Transistor gates suspected of floating are analyzed by expanding...
US20120110521 Split-Layer Design for Double Patterning Lithography  
A mechanism is provided for converting a set of single-layer design rules into a set of split-layer design rules for double patterning lithography (DPL). The set of single-layer design rules and...
US20140215426 ROUTING INTERCONNECT OF INTEGRATED CIRCUIT DESIGNS WITH VARYING GRID DENSITIES  
Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for...
US20120272201 METHOD AND SYSTEM FOR MODEL-BASED DESIGN AND LAYOUT OF AN INTEGRATED CIRCUIT  
A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of...