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US20090293033 System and method for layout design of integrated circuit  
A layout design system is provided with a storage device, a design processor, and an output device. The storage device stores interconnection-routed layout data of an integrated circuit. The design...
US20090293032 METHOD AND APPARATUS FOR CIRCUIT DESIGN AND RETIMING  
Methods and apparatuses to hierarchically retime a circuit. In at least one embodiment of the present invention. a module of a circuit is designed with a plurality of different latencies to have a...
US20090293031 Replicating Timing Data in Static Timing Analysis Operation  
An apparatus, method and program product create multiple copies of a clock signal, or phase, to analyze timing operations within a single timing run of a static timing analysis operation. At least...
US20090293030 Concurrently Modeling Delays Between Points in Static Timing Analysis Operation  
An apparatus, program product and method perform static timing analysis on an integrated circuit design by concurrently modeling a plurality of timing delays associated with a connection between...
US20090293029 SYSTEMATIC APPROACH FOR PERFORMING CELL REPLACEMENT IN A CIRCUIT TO MEET TIMING REQUIREMENTS  
An improved, systematic approach is provided for automatically determining which cells in a circuit should be replaced to satisfy timing adjustment requirements (TAR's), and automatically replacing...
US20090289696 Apparatus and Methods for Adjusting Performance of Integrated Circuits  
A programmable logic device (PLD) includes a delay circuit and a body-bias generator. The delay circuit has a delay configured to represent a delay of user circuit implement in the PLD. The...
US20090288052 METHOD AND APPARATUS FOR ANALYZING CIRCUIT  
In a circuit analyzing method, coordinate points of nodes in an analysis target circuit are detected from layout data of the analysis target circuit to store in a storage unit, and a minimum area...
US20090288051 METHODS FOR STATISTICAL SLEW PROPAGATION DURING BLOCK-BASED STATISTICAL STATIC TIMING ANALYSIS  
Methods for statistical slew propagation in static statistical timing analysis. The method includes projecting a canonical approximation of an input slew over a timing path to a first corner and...
US20090288050 Statistical delay and noise calculation considering cell and interconnect variations  
The electrical circuit timing method provides accurate nominal delay together with the delay sensitivities with respect to different circuit elements {e.g., cells, interconnects, etc.) and...
US20090282378 Semiconductor device design support apparatus and semiconductor device design support method  
A semiconductor device design support apparatus comprises: an input unit ( 101 ) which inputs layout information ( 108 ), LSI design information ( 109 ), switching information ( 110 ), a primitive...
US20090282377 VERIFICATION SUPPORT APPARATUS, VERIFICATION SUPPORT METHOD, AND COMPUTER PRODUCT  
An effective data amount and a power index of a module selected from a design target circuit are extracted from a time-series table DB for each clock cycle. Time periods during which the effective...
US20090282376 SIMULATION SYSTEM  
An extraction section extracts, in simulation of an operation of a circuit when it is assumed that a delay does not occur in a combination logic circuit, based on circuit information indicating a...
US20090276746 Circuit analysis method, semiconductor integrated circuit manufacturing method, circuit analysis program and circuit analyzer  
To perform a timing analysis at a high analysis accuracy while reducing a TAT. A circuit analyzer according to the present invention performs a timing analysis on a design target circuit after a...
US20090276745 DUMMY METAL INSERTION PROCESSING METHOD AND APPARATUS  
A method includes: before carrying out a timing verification processing of a semiconductor circuit, preliminarily superposing and arranging a dummy pattern template representing an arrangement...
US20090276744 OPERATION TIMING VERIFYING APPARATUS AND PROGRAM  
An operation timing verifying apparatus and program for accurately verifying operation timings of a semiconductor integrated circuit in design with suppressing design time and cost. The operation...
US20090276743 SYSTEM AND METHOD FOR COMPUTING PROXY SLACK DURING STATISTIC ANALYSIS OF DIGITAL INTEGRATED CIRCUITS  
A method of optimizing timing of signals within an integrated circuit design using proxy slack values propagates signals through the integrated circuit design to output timing signals. For early...
US20090271751 METHOD AND APPARATUS FOR STATISTICAL PATH SELECTION FOR AT-SPEED TESTING  
In one embodiment, the invention is a method and apparatus for statistical path selection for at-speed testing. One embodiment of a method for selecting a path of an integrated circuit chip for...
US20090271750 TIMING CONSTRAINT MERGING IN HIERARCHICAL SOC DESIGNS  
A method for propagating timing constraints from lower level design blocks to higher level design blocks includes o the steps of designing a circuit containing a plurality of design blocks. Each of...
US20090265674 METHODS FOR IDENTIFYING FAILING TIMING REQUIREMENTS IN A DIGITAL DESIGN  
Methods for identifying failing timing requirements in a digital design. The method includes identifying at least one timing test in the digital design that has a passing slack in a base process...
US20090259979 DESIGN TOOL AND METHOD FOR AUTOMATICALLY IDENTIFYING MINIMUM TIMING VIOLATION CORRECTIONS IN AN INTEGRATED CIRCUIT DESIGN  
A design tool for automatically identifying minimum timing violation corrections in an integrated circuit (IC) design includes program instructions executable by a processor to identify locations...
US20090254874 METHODS AND SYSTEMS FOR PLACEMENT AND ROUTING  
Techniques for placement of integrated circuit elements include global placement, detailed placement, timing closure, and routing. The integrated circuit is described by a netlist specifying...
US20090249272 STATISTICAL TIMING ANALYZER AND STATISTICAL TIMING ANALYSIS METHOD  
A statistical timing analyzer comprises a statistical static-timing analyzing unit that performs a statistical static timing analysis of a semiconductor integrated circuit; a corner-condition...
US20090249271 MICROCONTROLLER, CONTROL SYSTEM AND DESIGN METHOD OF MICROCONTROLLER  
Two data processing units having the same function, one of which is used for a master and the other for comparison, are provided, control of a circuit unit is performed by the master, the master...
US20090249270 METHODS FOR PRACTICAL WORST TEST DEFINITION AND DEBUG DURING BLOCK BASED STATISTICAL STATIC TIMING ANALYSIS  
Methods for analyzing timing of an integrated circuit using block-based static statistical timing analysis and for practical worst test definition and debug. The method includes building a timing...
US20090243393 SEMICONDUCTOR DEVICE, DESIGNING METHOD AND DESIGNING APPARATUS OF THE SAME  
A designing method of a semiconductor device includes: changing a power supply voltage changing a design data of a semiconductor device with a first power supply voltage into a design data of a...
US20090241081 REVERSE DONUT MODEL  
A pruning algorithm for generating a reverse donut model (RDM) for running timing analysis for a block in an IC includes logic to reduce a hierarchical model of the IC to a single level flat model....
US20090241080 SETUP AND HOLD TIME CHARACTERIZATION DEVICE AND METHOD  
A method of characterizing a device under test (DUT) includes determining a goal function associated with a setup and hold time for the DUT. A minimum value for the goal function is determined by...
US20090241079 METHOD AND SYSTEM FOR ACHIEVING POWER OPTIMIZATION IN A HIERARCHICAL NETLIST  
The invention generally relates to integrated circuit design, and more particularly to systems and methods for providing power optimization in a hierarchical netlist. A method includes generating a...
US20090241078 METHODS FOR CONSERVING MEMORY IN STATISTICAL STATIC TIMING ANALYSIS  
A method is provided for memory conservation in statistical static timing analysis. A timing graph is created with a timing run in a statistical static timing analysis program. A plurality of nodes...
US20090235218 TESTING PHASE ERROR OF MULTIPLE ON-DIE CLOCKS  
The phase relationship between two clock signals in an integrated circuit (IC) is determined by transforming each of the clock signals into a data word, where bit transitions in the data word...
US20090235217 METHOD TO IDENTIFY TIMING VIOLATIONS OUTSIDE OF MANUFACTURING SPECIFICATION LIMITS  
A method of evaluating an integrated circuit design selects manufacturing parameters of interest which are outside of manufacturing specification limits. Then, the method runs timing tests on the...
US20090228851 ARBITRARY WAVEFORM PROPAGATION THROUGH A LOGIC GATE USING TIMING ANALYSIS RESULTS  
An approach for performing arbitrary waveform propagation through a logic gate using timing analysis results is described. In one embodiment, there is an arbitrary waveform propagation tool for...
US20090228850 Method of modeling and employing the CMOS gate slew and output load dependent pin capacitance during timing analysis  
An accurate method to compute the capacitance at a pin whose capacitance is slew dependant. The method uses existing library characterized data and provides an equation based approach which can...
US20090224356 Method and apparatus for thermally aware design improvement  
Thermally aware design improvement enables increasing performance, reliability, and other related metrics by performing a multi-dimensional thermal analysis of a design of an electronic component...
US20090222781 METHOD FOR DESIGNING CIRCUIT LAYOUT CAPABLE OF PROPAGATING SIGNALS SYNCHRONOUSLY WITHOUT SIGNIFICANT ALTERATION OF LAYOUT  
In a circuit layout design method for designing an integrated circuit having signal lines synchronously propagating signals, delay correction cells having provisional values are inserted into the...
US20090222780 HALF CYCLE COMMON PATH PESSIMISM REMOVAL METHOD  
A design tool for reducing half-cycle common path pessimism includes program instructions storable on a computer readable medium. The program instructions may be executable by a processor to...
US20090222779 METHODS AND APPARATUSES FOR GENERATING A RANDOM SEQUENCE OF COMMANDS FOR A SEMICONDUCTOR DEVICE  
Methods and apparatuses for generating a random sequence of commands for a semiconductor device. The method generates random state transitions within a finite state machine model of the...
US20090217226 Multiple derating factor sets for delay calculation and library generation in multi-corner STA sign-off flow  
An apparatus and method to characterize a new process using an improved delay calculation. Multiple derating factors are used for different STA sign off corners that have a base corner with two...
US20090217225 MULTI-MODE MULTI-CORNER CLOCKTREE SYNTHESIS  
In one embodiment, a method for building a clock tree for an integrated circuit design is provided. The clock tree may include a clock tree root node and a plurality of clock tree nodes that couple...
US20090210841 STATIC TIMING ANALYSIS OF TEMPLATE-BASED ASYNCHRONOUS CIRCUITS  
Effective timing and power characterization flows are described for asynchronous circuits. Verification can be provided for both relative-timing constraints as well as performance (e.g.,...
US20090210840 Optimization Method of Integrated Circuit Design for Reduction of Global Clock Load and Balancing Clock Skew  
A design methodology and algorithms for the computer aided design of integrated circuits having clock distribution networks. The clustering of latch distribution tree components is combined with...
US20090210839 TIMING CLOSURE USING MULTIPLE TIMING RUNS WHICH DISTRIBUTE THE FREQUENCY OF IDENTIFIED FAILS PER TIMING CORNER  
A method of timing closure for integrated circuit designs uses multiple timing runs which distribute the frequency of identified fails per timing corner (between starting timing corners and...
US20090199144 Method of designing semiconductor integrated circuit having function to adjust delay pass and apparatus for supporting design thereof  
A power noise cycle is obtained from a dynamic IR drop analysis and a delay of a delay pass is a multiple of the noise cycle. Thereby, a delay increment and a delay decrement of a power noise...
US20090199143 CLOCK TREE SYNTHESIS GRAPHICAL USER INTERFACE  
In one embodiment, a method for performing an analysis of a synthesized clock tree can include: displaying a plurality of variation parameters and one or more analysis values on a display screen;...
US20090193375 MANUFACTURING METHOD, MANUFACTURING PROGRAM AND MANUFACTURING SYSTEM FOR SEMICONDUCTOR DEVICE  
The present of the invention provides a method of manufacturing a semiconductor device, including the steps of: acquiring information on a graphic composing a physical layout of a semiconductor...
US20090193374 METHOD OF DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, DESIGNING APPARATUS, AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE  
As a method for considering the adverse influence of the stresses caused form the pad, two sorts of methods are provided. As one method, while delay variation values of cells caused by an adverse...
US20090193373 MULTIPLE VOLTAGE THRESHOLD TIMING ANALYSIS FOR A DIGITAL INTEGRATED CIRCUIT  
An approach for performing multiple voltage threshold timing analysis for a digital integrated circuit is described. In one embodiment, there is a multiple voltage threshold timing analysis tool...
US20090187869 Budgeting Electromigration-Related Reliability Among Metal Paths In The Design Of A Circuit  
Apportioning unequally contributions of different metal paths of a circuit to electromigration (EM) reliability. In an embodiment, a corresponding parameter value representing a magnitude of excess...
US20090187868 DESIGN OF INTEGRATED CIRCUITS LESS SUSCEPTIBLE TO DEGRADATIONS IN TRANSISTORS CAUSED DUE TO OPERATIONAL STRESS  
According to an aspect of the present invention, statistical timing analysis is applied with respect to a stress degradation that occurs in fabricated integrated circuits (IC) when used for a long...
US20090172621 SYSTEM AND METHOD FOR SYSTEM-ON-CHIP (SOC) PERFORMANCE ANALYSIS  
A system and method of performing transaction level System on Chip (SoC) performance analysis includes obtaining a SoC description file including all intellectual property (IP) modules...
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