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US20090293025 |
SEMICONDUCTOR CIRCUIT DESIGN SUPPORT TECHNIQUE
Designation of observation points in an observation target circuit for which operations are observed in simulation is accepted, and circuit data of an observation circuit is attached to circuit...
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US20090293024 |
Detecting Circuit Design Limitations and Stresses Via Enhanced Waveform and Schematic Display
A method and apparatus are provided for implementing enhanced detection of circuit design limitations and stresses via enhanced waveform and schematic display. A selected simulation is run, for...
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US20090293023 |
Generation of standard cell library components with increased signal routing resources
Generating cells with increased signal routing resources. In an embodiment, power and ground buses in a metal layer of a source cell are identified and removed. Any vias terminating on the removed...
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US20090292383 |
SYSTEM AND METHOD FOR AUTOMATED ELECTRONIC DEVICE DESIGN
A system for the automated formation and control and execution of an electronic device design flow is disclosed which can enable more efficient electronic device design methodology with higher...
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US20090288049 |
Method for Rapid Estimation of Layout-Dependent Threshold Voltage Variation in a MOSFET Array
An automated method for estimating layout-induced variations in threshold voltage in an integrated circuit layout. The method begins with the steps of selecting a diffusion area within the layout...
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US20090288048 |
ANALYSIS OF STRESS IMPACT ON TRANSISTOR PERFORMANCE
Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of...
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US20090288047 |
METHOD AND APPARATUS FOR USING A DATABASE TO QUICKLY IDENTIFY AND CORRECT A MANUFACTURING PROBLEM AREA IN A LAYOUT
One embodiment provides a system for using a database to quickly identify a manufacturing problem area in a layout. During operation, the system receives a first check-figure which identifies a...
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US20090288046 |
CIRCUIT DESIGN PROCESSES
A method for designing a circuit. The method includes (i) providing a netlist of a design and (ii) dividing the netlist into N user logics, N being a positive integer. After said dividing the...
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US20090283892 |
Design method of semiconductor package substrate
When the impedance of a first circuit is deviated from a standard value, a second circuit is designed for generating a second reflected wave to cancel a first reflected wave generated by the first...
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US20090280582 |
Design Methodology for MuGFET ESD Protection Devices
A method for manufacturing a MuGFET ESD protection device having a given layout by means of a given manufacturing process, the method comprising selecting multiple interdependent layout and process...
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US20090276741 |
VERIFICATION SUPPORT APPARATUS, VERIFICATION SUPPORT METHOD, AND COMPUTER PRODUCT
In a verification support apparatus, an implementation description of a verification target is acquired and based on the implementation description, a combination of input gates is identified. A...
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US20090276737 |
TOOL FOR CHARGE TRAPPING MEMORY USING SIMULATED PROGRAMMING OPERATIONS
A method for simulating operation of a charge trapping memory cell which computes the amount of charge trapped by determining first tunneling current through the tunneling layer, determining second...
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US20090276736 |
Test Pattern Based Process Model Calibration
Embodiments of the present invention provide a method for performing lumped-process model calibration. The method includes creating a plurality of sub-process models for a set of sub-processes;...
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US20090276735 |
System and Method of Correcting Errors in SEM-Measurements
Embodiments of the invention relate to correcting errors in scanning electron measurements during measuring structural dimensions of an integrated circuit for optical proximity correction by...
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US20090256253 |
Continuously Referencing Signals Over Multiple Layers in Laminate Packages
A mechanism for continuously referencing signals over multiple layers in laminate packages provides a continuous path for signals from one layer to another while using the ideal voltage reference...
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US20090254872 |
Method for Designing and Manufacturing a PMOS Device with Drain Junction Breakdown Point Located for Reduced Drain Breakdown Voltage Walk-in
A PMOS device can be designed and manufactured in accordance with the invention to locate its drain junction breakdown point and maximum impact ionization point to reduce or eliminate drain...
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US20090254871 |
Methods for Hierarchical Noise Analysis
Systems and methods for hierarchical noise analysis of digital circuits, wherein analysis of a cell is based on the configuration of the cell itself and also the upstream circuit components that...
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US20090250778 |
PHOTOELECTRIC CONVERSION DEVICE, IMAGING SYSTEM, PHOTOELECTRIC CONVERSION DEVICE DESIGNING METHOD, AND PHOTOELECTRIC CONVERSION DEVICE MANUFACTURING METHOD
A photoelectric conversion device comprises a plurality of photoelectric conversion units, a first antireflection portion including a first insulation film which has a first refractive index and a...
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US20090249874 |
RATE-OF-TURN SENSOR
Disclosed is a method for driving and simultaneously determining the deflection (x(t)) and/or the rate of motion (v(t)) of an electrostatically excited oscillator element. According to said method,...
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US20090249266 |
Displacing Edge Segments On A Fabrication Layout Based On Proximity Effects Model Amplitudes For Correcting Proximity Effects
Techniques for forming a mask fabrication layout for a physical integrated circuit design layout include correcting the fabrication layout for proximity effects using a proximity effects model. A...
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US20090249265 |
PRINTED CIRCUIT BOARD DESIGNING APPARATUS AND PRINTED CIRCUIT BOARD DESIGNING METHOD
A method for designing a printed circuit board includes: determining a distance along a conductive line between an electronic component and a signal source which are mounted on the printed circuit...
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US20090249264 |
ANALYZING DEVICE FOR CIRCUIT DEVICE, CIRCUIT DEVICE ANALYZING METHOD, ANALYZING PROGRAM, AND ELECTRONIC MEDIUM
A circuit board analyzing method and a circuit board analyzer are provided which can greatly reduce analyzing time. The circuit board analyzer includes a computing unit 110, a memory unit 140 ...
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US20090249261 |
METHOD AND APPARATUS FOR OPTIMIZING AN OPTICAL PROXIMITY CORRECTION MODEL
A method includes receiving optical profiles for a plurality of design target features associated with an integrated circuit device and optical profiles for a plurality of test features. An optical...
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US20090241075 |
TEST CHIP VALIDATION AND DEVELOPMENT SYSTEM
Embodiments of an IC design system for test row/structure layout design are described in this application. The design system may include a test chip complier database, a test chip complier engine...
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US20090239313 |
Integrated Circuit Chip Design Flow Methodology Including Insertion of On-Chip or Scribe Line Wireless Process Monitoring and Feedback Circuitry
Disclosed are embodiments of a design and manufacturing system and an associated method that allow for design analysis and for insertion, during wafer manufacture, of intra-process monitoring...
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US20090236644 |
HIGH EFFICIENCY CMOS IMAGE SENSOR PIXEL EMPLOYING DYNAMIC VOLTAGE SUPPLY
A global shutter compatible pixel circuit comprising a reset gate (RG) transistor is provided in which a dynamic voltage is applied to the drain of the reset gate transistor in order to reduce a...
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US20090235213 |
Layout-Versus-Schematic Analysis For Symmetric Circuits
Techniques for reducing the complexity of Electronic Design Automation Layout-Versus-Schematic algorithms to approximately O(n) for graphs without type-3 symmetries.
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US20090235212 |
DESIGN STRUCTURE, FAILURE ANALYSIS TOOL AND METHOD OF DETERMINING WHITE BUMP LOCATION USING FAILURE ANALYSIS TOOL
A failure analysis tool, a method of using the tool and a design structure for designing a mask for protecting a critical area of wiring failure in a semiconductor chip during packaging is...
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US20090231087 |
RESISTOR AND DESIGN STRUCTURE HAVING SUBSTANTIALLY PARALLEL RESISTOR MATERIAL LENGTHS
A resistor and design structure including a pair of substantially parallel resistor material lengths separated by a first dielectric are disclosed. The resistor material lengths have a...
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US20090231085 |
RESISTOR AND DESIGN STRUCTURE HAVING RESISTOR MATERIAL LENGTH WITH SUB-LITHOGRAPHIC WIDTH
A resistor and design structure including at least one resistor material length in a dielectric, each of the least one resistor material length having a sub-lithographic width are disclosed.
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US20090228847 |
HIGH-FREQUENCY VLSI INTERCONNECT AND INTENTIONAL INDUCTOR IMPEDANCE EXTRACTION IN THE PRESENCE OF A MULTI-LAYER CONDUCTIVE SUBSTRATE
Embodiments of methods, apparatus, and systems for extracting impedance for a circuit design are disclosed herein. Some of the disclosed embodiments are computationally efficient and can accurately...
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US20090228846 |
GLOBAL STATISTICAL OPTIMIZATION, CHARACTERIZATION, AND DESIGN
For application to analog, mixed-signal, and custom digital circuits, a system and method to do: global statistical optimization (GSO), global statistical characterization (GSC), global statistical...
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US20090228845 |
Method, design program and design system for semiconductor device
A method of designing a semiconductor device includes: calculating a design value of a noise parameter based on design specification of the semiconductor device. The noise parameter contributes to...
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US20090222773 |
LEAKAGE CURRENT ANALYZING APPARATUS, LEAKAGE CURRENT ANALYZING METHOD, AND COMPUTER PRODUCT
A leakage current analyzing apparatus receives input of data used for analysis and indicating intra/inter-chip variation concerning the gate length of transistors constituting cells in a circuit to...
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US20090217222 |
SEMICONDUCTOR INTEGRATED CIRCUIT
A semiconductor integrated circuit includes: a plurality of processor elements each including a test circuit which tests whether there is a failure in the processor element and outputs a result of...
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US20090217221 |
SYSTEM AND METHOD TO OPTIMIZE SEMICONDUCTOR POWER BY INTEGRATION OF PHYSICAL DESIGN TIMING AND PRODUCT PERFORMANCE MEASUREMENTS
A system and method is provided for optimizing semiconductor power by integration of physical design timing and product performance measurements. The method includes: establishing a timing run and...
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US20090217220 |
METHOD OF DESIGNING AN ELECTRONIC DEVICE AND DEVICE THEREOF
A plurality of sequential nodes in a design file for an electronic device are identified and an effective switching capacitance is determined for a first sequential node of the plurality of...
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US20090217219 |
Method for designing an integrated circuit
A method for designing an integrated circuit is specified, in which upper and lower limits of dependent component parameters and of environment parameters ( 3, 4 ) are determined. The limits of the...
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US20090216512 |
Method and apparatus for indirectly simulating a semiconductor integrated circuit
A method and an apparatus for indirectly simulating a semiconductor integrated circuit (IC) are described. A circle chain is formed using input pins and output pins to provide an intellectual...
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US20090212854 |
Asymmetric Segmented Channel Transistors
Structures, layouts and methods of forming integrated circuits are described. In various embodiments, the current invention includes an asymmetric segmented transistor. The asymmetric segmented...
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US20090210832 |
Verification of Spare Latch Placement in Synthesized Macros
A method to assess spare latch placement in a macro, the method comprises steps of: determining a location for each spare latch in the macro; examining local clock buffers associated with the macro...
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US20090210831 |
CMOS Circuit Leakage Current Calculator
This invention provides a method for determining leakage current in a CMOS circuit having several devices. It includes the steps of reading a netlist which describes the circuit and includes...
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US20090210830 |
SYSTEM AND METHOD FOR ESTIMATING TEST ESCAPES IN INTEGRATED CIRCUITS
A method for designing an integrated circuit including estimating a test escape rate for tests of interest, a test coverage calculator and a system for estimating a test escape rate for tests of...
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US20090204930 |
IPHYSICAL DESIGN SYSTEM AND METHOD
A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and...
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US20090204365 |
MODELING SPATIAL CORRELATIONS
Modeling spatial correlations of semiconductor characteristic variations is disclosed. In one embodiment, a method includes developing a solution for each of a plurality of specific forms of...
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US20090201188 |
Semiconductor chip with a number of A/D converters that include a group of redundant A/D converters
The manufacturing yield of an A/D converter semiconductor chip is significantly increased by utilizing a number of A/D converter circuits that include a group of redundant A/D converter circuits....
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US20090199139 |
METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR IMPROVED ELECTRICAL ANALYSIS
An improved method, system, user interface, and computer program product is described for using a memory and learning component to improve capacitance and resistance estimates based on the types of...
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US20090199138 |
Method and Apparatus for Evaluating Integrated Circuit Design Model Performance Using Basic Block Vectors and Fly-By Vectors Including Microarchitecture Dependent Information
A test system or simulator includes an IC test application sampling software program that executes test application software on a semiconductor die IC design model. The test application sampling...
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US20090199137 |
SYSTEM AND METHOD FOR MULTI-EXPOSURE PATTERN DECOMPOSITION
Some embodiments provide a method and system for identifying error markers for patterns within a design layout that do not meet the manufacturing constraints. Some embodiments extend a region from...
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US20090193371 |
METHOD AND DEVICES TO ASSIST IN DETERMINING THE FEASIBILITY OF A COMPUTER SYSTEM
The invention concerns a method and devices for analyzing the feasibility of a computer system composed of subsystems, each having functions. After having determined the functional architecture of...
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