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US20090293022 Virtual Machine Placement Based on Power Calculations  
An optimized placement of virtual machines may be determined by optimizing an energy cost for a group of virtual machines in various configurations. For various hardware platforms, an energy cost...
US20090282374 Dummy Pattern Design for Reducing Device Performance Drift  
A method of forming an integrated circuit structure on a chip includes extracting an active pattern including a diffusion region; enlarging the active pattern to form a dummy-forbidden region...
US20090273408 FILTER DUPLEXER AND COMMUNICATION DEVICE  
A filter has a filter section that is provided with a balanced input terminal including a terminal 1 and a terminal 2 and a balanced output terminal including a terminal 3 and a terminal 4, ...
US20090271747 LOGIC CIRCUIT DESIGNING DEVICE, LOGIC CIRCUIT DESIGNING METHOD AND LOGIC CIRCUIT DESIGNING PROGRAM FOR ASYNCHRONOUS LOGIC CIRCUIT  
A logic circuit designing device for designing an asynchronous logic circuit which satisfies characteristic constraints of a state holding element represented by a latch or a flip-flop is provided....
US20090271746 METHOD OF CIRCUIT POWER TUNING THROUGH POST-PROCESS FLATTENING  
A method is provided for optimizing a hierarchical circuit design containing at least one reused cell. A first optimization is performed on the circuit design to meet a first objective. The first...
US20090267671 OPTIMIZATION OF LIBRARY SLEW RATIO BASED CIRCUIT  
Disclosed is a technique for providing minimal sequential overhead in a flip-flop circuit. Equalization of setup times is achieved in one embodiment. In addition, delays in clock to Q can be...
US20090262765 SMALL DIMENSION HIGH-EFFICIENCY HIGH-SPEED VERTICAL-CAVITY SURFACE-EMITTING LASERS  
A Vertical-Cavity Surface-Emitting Laser (VCSEL) is disclosed, comprising an optical cavity bounded by a top mirror and a bottom mirror, wherein the top mirror has multiple layers of alternating...
US20090254870 Automatic transistor arrangement device to arrange serially connected transistors, and method thereof  
When first and second hard macro transistors are arranged adjacently to each other, based on a circuit connection information and potentials of the first and second hard macro transistors are...
US20090249263 SEMICONDUCTOR CIRCUIT DESIGN METHOD AND SEMICONDUCTOR CIRCUIT MANUFACTURING METHOD  
A computer converts dimensions of design patterns of components of the transistors configuring the semiconductor circuit or component parameters extracted from in-design physical characteristics of...
US20090249262 BEHAVIORAL SYNTHESIS DEVICE, BEHAVIORAL SYNTHESIS METHOD, AND COMPUTER PROGRAM PRODUCT  
A behavioral synthesis device include a profile unit that implements an electronic circuit at a reconfigurable hardware based on a first register transfer level description generated by a...
US20090249261 METHOD AND APPARATUS FOR OPTIMIZING AN OPTICAL PROXIMITY CORRECTION MODEL  
A method includes receiving optical profiles for a plurality of design target features associated with an integrated circuit device and optical profiles for a plurality of test features. An optical...
US20090241073 Radiation Tolerance by Clock Signal Interleaving  
A method for designing integrated circuits uses clock signal interleaving to reduce the likelihood of a soft error arising from an upset in a clock distribution network. At least two circuits in a...
US20090235211 METHOD OF PREDICTING SUBSTRATE CURRENT IN HIGH VOLTAGE DEVICE  
A method of predicting a substrate current in a high voltage device that may accurately predict substrate current components in each of a first region, a second region, and a third region. This may...
US20090235210 ORIENTATION OPTIMIZATION METHOD OF 2-PIN LOGIC CELL  
In an orientation optimization, at least one signal chain path starting from a signal source and passing through a series of M 2-pin logic cells is located according to a netlist. An output of the...
US20090228844 METHOD FOR REDUCING POWER CONSUMPTION OF INTEGRATED CIRCUIT  
A method for reducing power consumption for an integrated circuit comprises the steps of (1) providing (i) a clock tree wherein the clock tree comprises a clock source, a plurality of clock sinks,...
US20090228843 METHOD TO OPTIMIZE POWER BY TUNING THE SELECTIVE VOLTAGE BINNING CUT POINT  
A method of optimizing power usage in an integrated circuit design analyzes multiple operating speed cut points that are expected to be produced by the integrated circuit design. The operating...
US20090222772 Power Gating Logic Cones  
Power gating logic cones is described. In one embodiment a method includes synthesizing logic for an integrated circuit (IC) design; identifying low switching nodes within the logic that switch...
US20090219051 HYBRID NANOTUBE/CMOS DYNAMICALLY RECONFIGURABLE ARCHITECTURE AND AN INTEGRATED DESIGN OPTIMIZATION METHOD AND SYSTEM THEREFOR  
A hybrid nanotube, high-performance, dynamically reconfigurable architecture, NATURE, is provided, and a design optimization flow method and system, NanoMap. A run-time reconfigurable architecture...
US20090217218 OPC SIMULATION MODEL USING SOCS DECOMPOSITION OF EDGE FRAGMENTS  
A system for estimating image intensity within a window area of a wafer using a SOCS decomposition to determine the horizontal and vertical edge fragments that correspond to objects within the...
US20090217217 METHOD OF CORRELATING SILICON STRESS TO DEVICE INSTANCE PARAMETERS FOR CIRCUIT SIMULATION  
Roughly described, standard SPICE models can be modified by substituting a different stress analyzer to better model the stress adjusted characteristics of a transistor. A first, standard,...
US20090217216 CARBON NANOTUBE CIRCUITS DESIGN METHODOLOGY  
A methodology is provided for optimizing circuit parameters of circuits including carbon nanotube transistors. The method comprises mapping ( 122 ) selected transistor design parameters ( 118 ),...
US20090212819 METHOD AND SYSTEM FOR CHANGING CIRCUITS IN AN INTEGRATED CIRCUIT  
A method for modifying an integrated circuit and integrated circuits are provided. The method includes: providing an integrated circuit design comprising a plurality of circuit books having a first...
US20090199136 Optimization of Integrated Circuit Design and Library  
A method co-optimizes a design and a library in such a way to choose the best set of cells to implement the design. The method takes into account the idea of limiting the number of new cells while...
US20090186424 PATTERN GENERATION METHOD, COMPUTER-READABLE RECORDING MEDIUM, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD  
A pattern generation method includes: acquiring a first design constraint for first patterns to be formed on a process target film by a first process, the first design constraint using, as indices,...
US20090178013 SYSTEM FOR IMPLEMENTING POST-SILICON IC DESIGN CHANGES  
An engineering change order (ECO) modifying an IC having spare cell instances is implemented by converting active cell instances implementing portions of the IC to be deleted into additional spare...
US20090178012 METHODOLOGY FOR IMPROVING DEVICE PERFORMANCE PREDICTION FROM EFFECTS OF ACTIVE AREA CORNER ROUNDING  
A system and method for modeling a semiconductor transistor device structure having a conductive line feature of a designed length connected to a gate of a transistor device in a circuit to be...
US20090174469 Sizing and Placement of Charge Recycling (CR) Transistors in Multithreshold Complementary Metal-Oxide-Semiconductor (MTCMOS) Circuits  
In one embodiment, a circuit includes a first row of circuit blocks that are each connected to a supply directly and to ground via a first sleep transistor. A connection between the first circuit...
US20090164954 AUTOMATIC ANTENNA DESIGNING APPARATUS AND AUTOMATIC ANTENNA DESIGNING METHOD  
An automatic antenna designing apparatus for designing a tag antenna of an IC tag, has a model storage unit configured to store models serving as templates of the tag antenna to be designed; and a...
US20090164953 Simultaneous optimization of analog design parameters using a cost function of responses  
An analog system consists of a multitude of interconnected components. Design of such a system involves optimization of the component parameters to achieve a target behavior, collectively called...
US20090158223 ADAPTIVE WEIGHTING METHOD FOR LAYOUT OPTIMIZATION WITH MULTIPLE PRIORITIES  
An adaptive weighting method for layout optimization differentiates different priorities by assigning the weight of a higher priority (p i ) to be multiple of the weight of a lower priority (p...
US20090144673 PARTIAL GOOD SCHEMA FOR INTEGRATED CIRCUITS HAVING PARALLEL EXECUTION UNITS  
Processing engines (PE's) disposed on the substrate. Each processing engine includes a measurement and storage unit, and a PE controller coupled to each of the processing engines. The processing...
US20090144672 DETERMINATION OF VALUES OF PHYSICAL PARAMETERS OF ONE OR SEVERAL COMPONENTS OF AN ELECTRONIC CIRCUIT OR OF A MICROELECTRO-MECHANICAL SYSTEM  
A method for determining, for each of at least p physical parameters of one or several components of an electronic circuit or of a microelectromechanical system, a number n of experiment values of...
US20090144671 DESIGNING INTEGRATED CIRCUITS FOR YIELD  
Method and system for designing integrated circuits for yield are described. Integrated circuits are designed for yield by finding worst yield corners based on design, statistical, and...
US20090144670 AUTOMATED OPTIMIZATION OF DEVICE STRUCTURE DURING CIRCUIT DESIGN STAGE  
A method of improving a circuit design for a very large scale integrated circuit is provided which represents a plurality of semiconductor devices interconnected in a circuit. It is determined...
US20090138833 METHOD, APPARATUS AND COMPUTER PROGRAM FOR FACILITATING THE IMPROVEMENT OF A USER INTERFACE  
There is disclosed a method, apparatus and computer program for facilitating improvement of a user interface. A plurality of critical paths though the user interface are determined. A complexity of...
US20090138832 IMPLEMENTING ENHANCED WIRING CAPABILITY FOR ELECTRONIC LAMINATE PACKAGES  
Structures and a computer program product are provided for implementing enhanced wiring capability for electronic laminate packages. Electronic package physical design data are received. Instances...
US20090132971 Structure for a Circuit Obtaining Desired Phase Locked Loop Duty Cycle without Pre-Scaler  
A design structure for a circuit for obtaining a desired phase locked loop (PLL) duty cycle without a pre-scaler is provided. The PLL circuit of the illustrative embodiments utilizes two separate...
US20090130821 THREE DIMENSIONAL PACKAGING WITH WAFER-LEVEL BONDING AND CHIP-LEVEL REPAIR  
A method, a system and a computer readable medium for three dimensional packaging with wafer-level bonding and chip-level repair. A first wafer is provided having a first plurality of chips. A...
US20090119621 Variability-Aware Asynchronous Scheme for Optimal-Performance Delay Matching  
A system for automatically transforming a given synchronous circuit description into an equivalent and provably correct desynchronized circuit description. Included in the automated transformation...
US20090113356 Optimization of Post-Layout Arrays of Cells for Accelerated Transistor Level Simulation  
A method for optimizing post-layout array for accelerated transistor level simulation is provided. In some embodiments of the present invention, a post-layout array of cells having a plurality...
US20090108899 DYNAMIC VOLTAGE SCALING FOR SELF-TIMED OR RACING PATHS  
A timing-constrained circuit (e.g., a self-timed circuit) of optimal performance is achieved by allowing the delay of the circuit to be changed dynamically as a function of operating conditions...
US20090106710 METHOD AND APPARATUS FOR SYNTHESIS  
Some embodiments of the invention provide a method for pre-tabulating sub-networks. This method (1) generates a sub-network that performs a function, (2) generates a parameter based on this...
US20090106709 System for Improving a Logic Circuit and Associated Methods  
A system for improving a logic circuit may include a processor, and a logic circuit analyzer in communication with the processor to model a plurality of nets. The system may also include an...
US20090100385 Optimal Simplification of Constraint-Based Testbenches  
Methods and systems are provided for determining redundancies in a system model such as a complex circuit design including gates that are state components. A candidate redundant gate is selected,...
US20090094565 METHOD AND DEVICE FOR SELECTIVELY ADDING TIMING MARGIN IN AN INTEGRATED CIRCUIT  
A method, system, and integrated circuit including selectively added timing margin. The method, for integrating statistical timing and automatic test pattern generation (ATPG) to selectively add...
US20090094564 METHOD FOR RAPID RETURN PATH TRACING  
A method for quickly tracing minimum-length conductive return paths through an electronic structure utilizes a raster based (cellular) memory model comprising individual grids for each layer of the...
US20090083679 Efficient Second Harmonic Generation (SHG) Laser Design  
A method, a data processing method, and a computer program product for the design of efficient second harmonic generation semiconductor lasers is disclosed. A method for determining an optimum...
US20090083599 Hierarchical test response compaction for a plurality of logic blocks  
In one embodiment, the present invention includes first level matrices, each including m input terminals and n output terminals, each coupled to a processor core, and second level matrices each...
US20090077506 Simultaneous Multi-Layer Fill Generation  
Techniques are disclosed for optimizing the pattern density in the circuit layout design of a circuit layer. A layer in circuit design is analyzed to define empty regions that can be filled with...
US20090070716 SYSTEM AND METHOD FOR OPTIMIZATION AND PREDICATION OF VARIABILITY AND YIELD IN INTEGRATED CIRUITS  
A system and method for designing a circuit includes generating physics based equations to describe phenomena of a circuit component, representing physical device geometry by correlating the...
Matches 1 - 50 out of 161 1 2 3 4 >