Matches 1 - 34 out of 34
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US20090300562 Design structure for out of band signaling enhancement for high speed serial driver  
A design structure is provided for a microelectronic serial driver. The serial driver is operable to transmit a differential pattern signal during a burst interval and a predetermined common mode...
US20090288055 Method and system for characterizing an integrated circuit design  
A method and a system for characterizing an integrated circuit (IC) design are disclosed. The method includes receiving a description of leaf cells used in the IC design. The IC design is described...
US20090271756 Minimal Leakage-Power Standard Cell Library  
A minimal leakage power Standard Cell Library is provided. The minimal leakage power Standard Cell Library provides minimal leakage power cells with improved speed characteristics. The minimal...
US20090271753 Methods for Cell Phasing and Placement in Dynamic Array Architecture and Implementation of the Same  
A semiconductor chip is defined to include a logic block area having a first chip level in which layout features are placed according to a first virtual grate, and a second chip level in which...
US20090265678 System and Method of Resistance Based Memory Circuit Parameter Adjustment  
Systems and methods of resistance based memory circuit parameter adjustment are disclosed. In a particular embodiment, a method of determining a set of parameters of a resistance based memory...
US20090235222 CREATING A STANDARD CELL CIRCUIT DESIGN FROM A PROGRAMMABLE LOGIC DEVICE CIRCUIT DESIGN  
A computer-implemented method of converting a circuit design for a programmable logic device (PLD) to a standard cell circuit design can include unmapping a PLD circuit design to a gate level...
US20090212818 Integrated circuit design method for improved testability  
An integrated circuit design method includes: classifying flipflops arranged around a macro based on a netlist of a integrated circuit incorporating the flipflops and the macro; and generating a...
US20090212327 STANDARD CELL LIBRARIES AND INTEGRATED CIRCUIT INCLUDING STANDARD CELLS  
A standard cell library includes a first power rail, a second power rail, a third power rail, a first standard cell, and second standard cells. The first power rail extends in a first direction....
US20090201758 Method for designing integrated circuit incorporating memory macro  
An integrated circuit design method is provided in which memory instances are assigned to memory macros integrated within an integrated circuit. The integrated circuit design method includes:...
US20090193384 SHIFT-ENABLED RECONFIGURABLE DEVICE  
A coarse-grain reconfigurable array that implements shift operations within its interconnection network is disclosed. The interconnection network of such a coarse-grain reconfigurable array...
US20090183136 Structure for a Programmable Interpolative Voltage Controlled Oscillator with Adjustable Range  
A design structure for a programmable interpolative voltage controlled oscillator (VCO) with adjustable frequency range output is provided. Programmable delay cells whose size is modifiable based...
US20090183135 Method and Device for Identifying and Implementing Flexible Logic Block Logic for Easy Engineering Changes  
A chip design methodology. The methodology includes identifying engineering changeable logic, and replacing the identified engineering changeable logic with flexible logic blocks (FLB).
US20090160483 Field programmable application specific integrated circuit with programmable logic array and method of designing and programming the programmable logic array  
A programmable logic array for use in a field programmable application specific integrated circuit (ASIC) implementation is provided. The programmable logic array includes programmable logic...
US20090144689 Structure for a Voltage Detection Circuit in an Integrated Circuit and Method of Generating a Trigger Flag Signal  
A design structure for an integrated circuit that includes at least one tunneling device voltage detection circuit for generating a trigger flag signal. The tunneling device voltage detection...
US20090138841 SYSTEM AND APPARATUS FOR IN-SYSTEM PROGRAMMING  
Embodiments of the present invention relate to machines that perform in-system programming of programmable devices that are attached to assembled printed circuit boards. In accordance with one...
US20090101940 DUAL GATE FET STRUCTURES FOR FLEXIBLE GATE ARRAY DESIGN METHODOLOGIES  
A gate array cell adapted for standard cell design methodology or programmable gate array that incorporates a dual gate FET device to offer a range of performance options within the same unit cell...
US20090083681 Methods and apparatuses for designing integrated circuits using virtual cells  
Methods and apparatuses for analyzing and/or designing integrated circuits using virtual transparent cells disclosed. Some embodiments comprise calculating model values for virtual transparent...
US20090077513 GENERALIZED CONSTRAINT COLLECTION MANAGEMENT METHOD  
Techniques are provided to allow users of Electronic Design Automation (EDA) tools to define constraint template types for efficiently associating constraints with design objects to specify design...
US20090070727 Three dimensional integrated circuits and methods of fabrication  
Three dimensional integrated circuitry is described with applications to hybrid multiprocessor and reconfigurable computing. Methods of fabrication of multilayer ICs are shown using multilayer TSVs.
US20090045841 Method for Radiation Tolerance by Implant Well Notching  
A logic book for a programmable device such as an application-specific integrated circuit (ASIC) achieves improved radiation tolerance by providing notches in an implant well between adjacent...
US20090044165 FPGA with hybrid interconnect  
An Application-Specific Field Programmable Gate Array (FPGA) device or fabric is described for use in applications requiring fast reconfigurability of devices in the field, enabling multiple...
US20080301619 SYSTEM AND METHOD FOR PERFORMING NEXT PLACEMENTS AND PRUNING OF DISALLOWED PLACEMENTS FOR PROGRAMMING AN INTEGRATED CIRCUIT  
A system and method for graphically displaying modules and resources within a chip design software application. The system and method provide a data driven model for matching the hardware resource...
US20080295057 METHOD FOR DETERMINING A STANDARD CELL FOR IC DESIGN  
IC design flow includes RTL design, synthesis, APR, and layout. An IC designer can choose a suitable standard cell for an integrated circuit according to the timing, area, and BCI (best cell index)...
US20080295056 System and Method for Building Configurable Designs with Hardware Description and Verification Languages  
An invention is provided for building configurable designs synthesizable to gates. The invention includes creating a configurable design using an HDL. The configurable design has a plurality of...
US20080288910 STRUCTURE FOR ESTIMATING POWER CONSUMPTION OF INTEGRATED CIRCUITRY  
A design structure is embodied in a machine readable medium for designing, manufacturing, or testing integrated circuitry. The design structure includes first hardware for executing first software...
US20080282215 METHOD OF DESIGNING A DIGITAL INTEGRATED CIRCUIT FOR A MULTI-FUNCTIONAL DIGITAL PROTECTIVE RELAY  
This invention relates to a method of designing a digital integrated circuit for a multi-functional digital protective relay, emphasizing a digital module part, and input voltage and current...
US20080163151 Method For The Definition Of A Library Of Application-Domain-Specific Logic Cells  
The present invention provides in one aspect a method of defining a logic cell library composed of complex functions and simple functions, with some of the complex functions obtained from...
US20080148210 INTEGRATED CIRCUIT SELECTIVE SCALING  
The invention includes a solution for selectively scaling an integrated circuit (IC) design by: layer, region or cell, or a combination of these. The selective scaling technique can be applied in a...
US20080134127 METHODS AND APPARATUS FOR IMPLEMENTING PARAMETERIZABLE PROCESSORS AND PERIPHERALS  
Methods and apparatus are provided for implementing parameterizable processor cores and peripherals on a programmable chip. An input interface such as a wizard allows selection and parameterization...
US20080134120 SEMICONDUCTOR LAYOUT DESIGN APPARATUS, SEMICONDUCTOR LAYOUT DESIGN METHOD AND COMPUTER READABLE MEDIUM  
A semiconductor layout design apparatus has an inter-block connection information extracting part, a block global placement part and a cell placement setting part. The inter-block connection...
US20080127018 Clock Aware Placement  
The layout of latches in a common clock domain is efficiently optimized to shrink the physical size of the domain while maintaining timing requirements. The latches are placed in a first layout...
US20080082951 Structure Cluster and Method in Programmable Logic Circuit  
A method for clustering logic units in a field programmable integrated chip to generate a set of clusters is disclosed. The clustering step for forming a super cluster comprises a first logic...
US20080028355 METHOD AND SOFTWARE TOOL FOR DESIGNING AN INTEGRATED CIRCUIT  
A method of designing an integrated circuit for an application having standards having a plurality of primitives, each of the primitives having a corresponding response. The method includes...
US20080016486 System and method of assessing reliability of a semiconductor  
A system for assessing reliability of a semiconductor product design, the system comprising a first database for storing circuits data specifying cells of available circuits for semiconductor...
Matches 1 - 34 out of 34