Matches 1 - 43 out of 43


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US20150046895 VLSI Layouts of Fully Connected Generalized and Pyramid Networks with Locality Exploitation  
VLSI layouts of generalized multi-stage and pyramid networks for broadcast, unicast and multicast connections are presented using only horizontal and vertical links with spacial locality...
US20140047405 Method and Apparatus for Implementing Soft Constraints in Tools Used for Designing Programmable Logic Devices  
A method for designing a system on a target device utilizing programmable logic devices (PLDs) includes generating options for utilizing resources on the PLDs in response to user specified...
US20090009215 Integrated Circuit with Multidimensional Switch Topology  
An FPGA needs extremely large numbers of switches in its wiring architecture and therefore shows low logic density and low operating speed. This tendency becomes increasingly evident with high...
US20090070728 IP cores in reconfigurable three dimensional integrated circuits  
The invention describes IP cores applied to 3D FPGAs, CPLDs and reprogrammable SoCs. IP cores are (a) used for continuously evolvable hardware using 3D logic circuits, (b) applied with...
US20090235222 CREATING A STANDARD CELL CIRCUIT DESIGN FROM A PROGRAMMABLE LOGIC DEVICE CIRCUIT DESIGN  
A computer-implemented method of converting a circuit design for a programmable logic device (PLD) to a standard cell circuit design can include unmapping a PLD circuit design to a gate level...
US20110225560 LOGIC SYSTEM FOR DPA RESISTANCE AND/OR SIDE CHANNEL ATTACK RESISTANCE  
DPA-resistant logic circuits and routing are described. An architecture and methodology are suitable for integration in a common automated EDA design tool flow. The architecture and design...
US20060225020 Methods and apparatus for 3-D FPGA design  
Methods, apparatus, and systems are directed to an FPGA that includes a three-dimensional architecture having a component coupled to at least five components across two or more strata. In one...
US20140089885 ELECTRONIC CIRCUIT DESIGN METHOD  
A first assembly of critical cells is to be monitored. An equivalent capacitance of output cells coupled to the critical path is determined. Logic level inputs of the critical cells for signal...
US20080209385 Mapping Programmable Logic Devices  
Methods and systems improve mapping of LUT based FPGAs. In some embodiments, a topological sort is performed on a network to be mapped, whereby the network is represented as a Directed Acyclic...
US20090193384 SHIFT-ENABLED RECONFIGURABLE DEVICE  
A coarse-grain reconfigurable array that implements shift operations within its interconnection network is disclosed. The interconnection network of such a coarse-grain reconfigurable array...
US20080288909 Template-Based Domain-Specific Reconfigurable Logic  
A method is provided which creates an architecture of a reconfigurable logic core. The architecture can be deployed for various purposes and its implementation is costefficient in terms of area,...
US20090101940 DUAL GATE FET STRUCTURES FOR FLEXIBLE GATE ARRAY DESIGN METHODOLOGIES  
A gate array cell adapted for standard cell design methodology or programmable gate array that incorporates a dual gate FET device to offer a range of performance options within the same unit cell...
US20080034341 Methods and computer readable media implementing a modified routing grid to increase routing densities of customizable logic array devices  
Disclosed are a method and a computer readable medium for increasing routing density in cells of a customizable logic array device. In one embodiment, the method includes modifying a connectivity...
US20090249276 METHODS AND SYSTEMS FOR FPGA REWIRING AND ROUTING IN EDA DESIGNS  
Disclosed are a method and a system for improving FPGA routings of a circuit. The method comprises: identifying candidate alternative wires for a target wire to be replaced in the circuit...
US20100058274 FLEXIBLE HARDWARE UPGRADE MECHANISM FOR DATA COMMUNICATIONS EQUIPMENT  
Partial reconfiguration of programmable logic devices may be achieved in a hardware-controlled manner without relying upon software. Upon installation of a new memory module, partial...
US20070157150 Base project resource management and application synthesis  
In one embodiment, a method for constructing an application includes detecting a change to a design of an application, evaluating the design against hardware resources associated with application...
US20070157149 Design configuration method for an automation system  
The invention relates to a projection method for an automation system, in addition to a device which is used to project an automation system. In order to simplify the projection of an automation...
US20070143729 High speed camera bandwidth converter  
Image data from a CMOS sensor with 10 bit resolution is reformatted to allow the data to pass through communications equipment that is designed to transport data with 8 bit resolution. The...
US20090300571 METHODS AND SYSTEMS FOR FPGA REWIRING  
There are disclosed a method and system for FPGA rewiring of a circuit. The method comprises: mapping the circuit into a first circuit, the first circuit being logically represented with a...
US20130334576 Gate array architecture with multiple programmable regions  
An integrated circuit includes a gate array layer having a two-dimensional array of logic gates, each logic gate including multiple transistors. At least one upper template-based metal layer is...
US20120227026 Method and Apparatus for Placement and Routing of Partial Reconfiguration Modules  
A method for designing a system on a target device includes assigning resources on the target device to static logic modules and partial reconfigurable (PR) modules in the system. The instances of...
US20090070727 Three dimensional integrated circuits and methods of fabrication  
Three dimensional integrated circuitry is described with applications to hybrid multiprocessor and reconfigurable computing. Methods of fabrication of multilayer ICs are shown using multilayer TSVs.
US20100155775 Design Structure and Method for an Electrostatic Discharge (ESD) Silicon Controlled Rectifier (SCR) Structure  
A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes first and second silicon controlled rectifiers (SCRs)...
US20100070942 Automated Metal Pattern Generation for Integrated Circuits  
An integrated circuit fabricated by a mask set including a mask to generate a metal pattern defined by CAD software, the metal pattern generation method including: reading a binary data set, the...
US20100207659 FIELD PROGRAMMABLE GATE ARRAY WITH INTEGRATED APPLICATION SPECIFIC INTEGRATED CIRCUIT FABRIC  
A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or...
US20100231263 Logic Circuit and Method of Logic Circuit Design  
A complementary logic circuit contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a high-voltage terminal configured for...
US20090160482 Formation of a hybrid integrated circuit device  
Formation of a hybrid integrated circuit device (400) is described. A design for the integrated circuit (100) is obtained and separated into at least two portions responsive to component sizes. A...
US20140237441 Method and Apparatus for Placing and Routing Partial Reconfiguration Modules  
A method for designing a system on a target device includes assigning resources on the target device to static logic modules and partial reconfigurable (PR) modules in the system. The instances of...
US20090288057 System and Method for Ordering the Selection of Integrated Circuit Chips  
A routing engine for use with a mounter having a chip selector and a method of routing a chip selector of a mounter. In one embodiment, the routing engine includes: (1) a memory configured to...
US20100017774 METHOD AND SYSTEM FOR MOUNTING CIRCUIT DESIGN ON RECONFIGURABLE DEVICE  
There is provided a system for generating configuration data for implementing a circuit design in a segmented reconfigurable device. A placement and routing design aiding system (30) includes a...
US20140351782 Program Binding System, Method and Software for a Resilient Integrated Circuit Architecture  
The exemplary embodiments provide a program binder for a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a...
US20080282214 RECONFIGURABLE INTEGRATED CIRCUIT  
The purpose of the present invention is to realize reduction of power consumption of reconfigurable integrated circuits such as FPGAs by decreasing leakage current in SRAMs. A reconfigurable...
US20080244500 System, methods and apparatuses for integrated circuits for nanorobotics  
The invention describes apparatuses for nano-scale integrated circuits applied to nanorobotics. Using EDA techniques, the system develops fully functional nano ICs, including ASICs and...
US20100218158 METHOD AND APPARATUS FOR CAMOUFLAGING A STANDARD CELL BASED INTEGRATED CIRCUIT  
A method and apparatus for camouflaging an application specific integrated circuit (ASIC), wherein the ASIC comprises a plurality of interconnected functional logic is disclosed. The method adds...
US20100155855 Band Edge Engineered Vt Offset Device  
Band edge engineered Vt offset devices, design structures for band edge engineered Vt offset devices and methods of fabricating such structures is provided herein. The structure includes a first...
US20100199254 Programmable analog tile programming tool  
A programmable analog tile integrated circuit programming tool communicates a power management control characteristic query soliciting control requirement information for a novel power management...
US20100333058 METHOD FOR INCREASING THE MANUFACTURING YIELD OF PROGRAMMABLE LOGIC DEVICES  
A method for increasing the manufacturing yield of field programmable gate arrays (FPGAs) or other programmable logic devices (PLDs). An FPGA or other PLD is formed in several sections, each of...
US20100138803 APPARATUS AND METHOD OF SUPPORTING DESIGN OF SEMICONDUCTOR INTEGRATED CIRCUIT  
A method of supporting design of a semiconductor integrated circuit, is achieved by generating a data indicating a basic cell and a data indicating a cell group different in logic from the basic...
US20100230779 TRENCH GENERATED DEVICE STRUCTURES AND DESIGN STRUCTURES FOR RADIOFREQUENCY AND BICMOS INTEGRATED CIRCUITS  
Trench-generated device structures fabricated using a semiconductor-on-insulator (SOI) wafer, design structures embodied in a machine readable medium for designing, manufacturing, or testing an...
US20100138804 Methods and Apparatuses for Automated Circuit Design  
Methods and apparatuses to automatically synthesize circuits. In one aspect of an embodiment, a logic function feeding a carry chain is implemented through extending the carry chain and through...
US20160275230 REPEATER INSERTIONS PROVIDING REDUCED ROUTING PERTURBATION CAUSED BY FLIP-FLOP INSERTIONS  
System and method of automatically performing repeater insertions in physical design of an integrated circuit. Repeaters are inserted in interconnects in a staggered fashion and spaced apart to...
US20160063168 PATTERN-BASED FPGA LOGIC BLOCK AND CLUSTERING ALGORITHM  
A routing architecture for fast interconnections between Look-Up Tables (LUTs) in a group of Basic Logic Elements (BLEs), whereby a size of the group ranges from 1 to k+1, where k is the number of...
US20110107290 VARIABLE SIZED SOFT MEMORY MACROS IN STRUCTURED CELL ARRAYS, AND RELATED METHODS  
The logic cells (HLEs) of a structured application-specific integrated circuit (structured ASIC) can be used to provide memory blocks of various sizes. Any one or more of several techniques may be...

Matches 1 - 43 out of 43