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US20090300570 |
INTERACTIVE HIERARCHICAL ANALOG LAYOUT SYNTHESIS FOR INTEGRATED CIRCUITS
In one embodiment of the invention, a method of synthesizing a layout of an integrated circuit chip including analog circuitry is disclosed. The method includes receiving a circuit netlist of an...
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US20090293033 |
System and method for layout design of integrated circuit
A layout design system is provided with a storage device, a design processor, and an output device. The storage device stores interconnection-routed layout data of an integrated circuit. The design...
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US20090293023 |
Generation of standard cell library components with increased signal routing resources
Generating cells with increased signal routing resources. In an embodiment, power and ground buses in a metal layer of a source cell are identified and removed. Any vias terminating on the removed...
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US20090278263 |
RELIABILITY WCSP LAYOUTS
An integrated circuit device includes a functional circuit die with a patterned rewiring layer defining a first rewiring pad and one or more second rewiring pads on opposite sides of a neutral...
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US20090278185 |
DEVICE STRUCTURES FOR A MEMORY CELL OF A NON-VOLATILE RANDOM ACCESS MEMORY AND DESIGN STRUCTURES FOR A NON-VOLATILE RANDOM ACCESS MEMORY
Device and design structures for memory cells in a non-volatile random access memory (NVRAM). The device structure includes a semiconductor body in direct contact with the insulating layer, a...
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US20090276742 |
AUTOMATING POWER DOMAINS IN ELECTRONIC DESIGN AUTOMATION
One or more portions of the design (e.g., components, channels, or portions thereof) can be assigned instances of one or more component power domains (CPDs). Assigning an instance of a CPD to a...
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US20090258302 |
SUB-RESOLUTION ASSIST FEATURE OF A PHOTOMASK
A photomask including a main feature, corresponding to an integrated circuit feature, and a sub-resolution assist feature (SRAF) is provided. A first imaginary line tangential with a first edge of...
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US20090251848 |
DESIGN STRUCTURE FOR METAL-INSULATOR-METAL CAPACITOR USING VIA AS TOP PLATE AND METHOD FOR FORMING
A design structure for a metal-insulator-metal (MIM) capacitor using a via as a top plate and method for forming is described. In one embodiment, the MIM capacitor structure comprises a bottom...
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US20090241075 |
TEST CHIP VALIDATION AND DEVELOPMENT SYSTEM
Embodiments of an IC design system for test row/structure layout design are described in this application. The design system may include a test chip complier database, a test chip complier engine...
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US20090228846 |
GLOBAL STATISTICAL OPTIMIZATION, CHARACTERIZATION, AND DESIGN
For application to analog, mixed-signal, and custom digital circuits, a system and method to do: global statistical optimization (GSO), global statistical characterization (GSC), global statistical...
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US20090224334 |
Merged Field Effect Transistor Cells For Switching
Disclosed are embodiments of an improved integrated circuit switching device that incorporates multiple sets of series connected field effect transistors with each set further connected in parallel...
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US20090210846 |
I/O PLANNING WITH LOCK AND INSERTION FEATURES
A method of operation for an input/output assignment tool is disclosed. The method generally includes the steps of (A) generating a graphic presentation to a user displaying (i) a circuit icon...
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US20090210845 |
COMPUTER PROGRAM PRODUCT, APPARATUS, AND METHOD FOR INSERTING COMPONENTS IN A HIERARCHICAL CHIP DESIGN
Components are inserted into a cell-based current chin design with multiple levels of nested hierarchy. A selection of components having various silicon densities to insert into the current chip...
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US20090200875 |
Apparatus for supporting design of semiconductor integrated circuit device and method for designing semiconductor integrated circuit device
A semiconductor integrated circuit device includes: a first power supply region, power supply to which is controlled; and a second power supply region connected with a first power supply region....
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US20090199147 |
LAYOUT DATA REDUCTION FOR USE WITH ELECTRONIC DESIGN AUTOMATION TOOLS
A system and method which stores a three dimensional physical representation of an electrical circuit such as an integrated circuit design uses a database having a plurality of files to store...
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US20090199143 |
CLOCK TREE SYNTHESIS GRAPHICAL USER INTERFACE
In one embodiment, a method for performing an analysis of a synthesized clock tree can include: displaying a plurality of variation parameters and one or more analysis values on a display screen;...
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US20090189641 |
INTEGRATED CIRCUIT DEVICE AND LAYOUT DESIGN METHOD THEREFOR
An integrated circuit device has multiple first circuit elements arranged in a first area. A signal distribution circuit that has multiple drive circuits is connected in the form of a tree...
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US20090187871 |
Hierarchical Compression For Metal One Logic Layer
A method of increasing hierarchy compression of a metal 1 standard cell layout during optical proximity correction (OPC) is provided. This method can use a context determination defined from the...
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US20090183134 |
DESIGN STRUCTURE FOR IDENTIFYING AND IMPLEMENTING FLEXIBLE LOGIC BLOCK LOGIC FOR EASY ENGINEERING CHANGES
A design structure for identifying engineering changeable logic, and replacing the identified engineering changeable logic with flexible logic blocks (FLB). The design structure is embodied in a...
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US20090183133 |
TOOL AND METHOD TO GRAPHICALLY CORRELATE PROCESS AND TEST DATA WITH SPECIFIC CHIPS ON A WAFER
A tool and method is provided to graphically correlate process and test data with specific chips on a multi-project wafer. The tool and method is configured and implemented to select certain sites...
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US20090172627 |
Design Structure for a Clock System for a Plurality of Functional Blocks
A design structure for a clock system for a plurality of functional blocks designed using a method of reducing peak power that utilizes connectivity and/or timing information among a plurality of...
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US20090172626 |
METHOD AND SYSTEM FOR VISUAL IMPLEMENTATION OF LAYOUT STRUCTURES FOR AN INTEGRATED CIRCUIT
The present approach is directed to an improved method, system, and computer program product for visually presenting layout options for generating an electronic design. The visual presentation...
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US20090164962 |
Method of Reducing Crosstalk Induced Noise in Circuitry Designs
A method of reducing crosstalk induced noise in a physical circuit wiring design constructs a spatial vector for each interconnect wire segment in the physical circuit wiring design. The method...
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US20090164961 |
Design Structure for a System For Controlling Access to Addressable Integrated Circuits
A design structure for a circuitry access system for controlling access to addressable circuit elements of an integrated circuit. The circuitry access system includes a first storage element having...
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US20090150847 |
Logic circuit delay optimization
A method for modifying a logic circuit layout to optimize circuit propagation delays for improved circuit operation is presented. The layout includes multiple logic gates connected by conductive...
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US20090132987 |
Method and system for the modular design and layout of integrated circuits
An integrated circuit (IC) and fabrication method thereof is provided that include the steps of specifying a plurality of required tile modules suitable for a particular end application, each of...
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US20090132986 |
CIRCUIT DESIGN ASSISTING APPARATUS, METHOD, AND PROGRAM
A circuit design assisting apparatus for assisting a layout tool in designing an integrated circuit that includes a circuit module having plural cells achieving a prescribed function. A cell...
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US20090125852 |
METHOD AND APPARATUS FOR NET-AWARE CRITICAL AREA EXTRACTION
In one embodiment, the present invention is a method and apparatus for net-aware critical area extraction. One embodiment of the inventive method for determining the critical area of an integrated...
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US20090119633 |
CAD APPARATUS AND PROGRAM USED IN THE SAME
A CAD apparatus is comprised of: input unit 102 A for inputting design input information of the component model by a CAD operator; sequence information storage unit 105 A for previously storing...
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US20090113370 |
Layout designing method for semiconductor device and layout design supporting apparatus for the same
In a layout designing method of a semiconductor device, a first standard cell with a first well and a second standard cell with a second well are arranged. The first well and the second well are...
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US20090113369 |
REGISTRY FOR ELECTRONIC DESIGN AUTOMATION OF INTEGRATED CIRCUITS
A method for registering constraints for EDA (Electronic Design Automation) of an IC (Integrated circuit) includes: associating a constraint with values for constraint identification that identify...
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US20090089734 |
METHOD FOR FASTER IDENTIFICATION OF AVAILABLE REFERENCE DESIGNATORS IN A DESIGN AUTOMATION SYSTEM
A method, system, and computer program product for a faster identification of available reference designators (ARDs) in a design automation system. An ARD utility detects a selection of one or more...
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US20090089733 |
METHOD FOR AUTOMATICALLY PRODUCING LAYOUT INFORMATION
A method of automatically producing layout information includes receiving first layout information of an integrated circuit; when receiving the first layout information, activating an automated...
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US20090083688 |
METHOD AND APPARATUS FOR GENERATING A LAYOUT FOR A TRANSISTOR
A system that generates a layout for a transistor is presented. During operation, the system receives a transistor library which includes operating characteristics of fabricated transistors...
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US20090077519 |
Displacement Aware Optical Proximity Correction For Microcircuit Layout Designs
Techniques for adjusting edge segments within a layout design such that fewer iterations of an optical proximity correction process are required for covergence are provided. With various...
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US20090077518 |
DERIVED LEVEL RECOGNITION IN A LAYOUT EDITOR
A computer program product stored on machine readable media includes machine executable instructions for displaying a layout of a circuit design, the product including instructions for: over a...
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US20090073621 |
Fast Triggering ESD Protection Device and Method for Designing Same
A method and apparatus for designing an ESD protection circuit comprising a main ESD device and a triggering device connected to a triggering node of the main ESD device by means of which the main...
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US20090070724 |
INFORMATION PROCESSING DEVICE, METHOD OF CREATING POWER SUPPLY SYSTEM TREE AND PROGRAM OF THE SAME
According to one embodiment, an information processing device includes a registration section for registering terminals of a symbol diagrams to a library by associating a relationship of...
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US20090070723 |
METHOD FOR GENERATING A SCAN CHAIN IN A CUSTOM ELECTRONIC CIRCUIT DESIGN
The present invention relates to a method for generating a scan chain in a custom electronic circuit design with a plurality of storage elements. Said method comprises the steps of providing a...
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US20090064078 |
Method of designing a semiconductor integrated circuit having a dummy area and the semiconductor integrated circuit thereof
An exemplary semiconductor integrated circuit is formed on a surface of a semiconductor chip includes a circuit region and a dummy region on the surface of the semiconductor chip. The circuit...
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US20090064077 |
LAYOUT VERSUS SCHEMATIC ERROR SYSTEM AND METHOD
According to various embodiments of the invention, systems and methods for presenting Layout Versus Schematic (LVS) errors within a layout using a visual circuit representation of the design and...
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US20090064076 |
SYSTEMS, METHODS AND COMPUTER PRODUCTS FOR TRAVERSING SCHEMATIC HIERARCHY USING A SCROLLING MECHANISM
A method and a system for displaying hierarchical navigating, debugging and editing of selected hierarchical levels of design of a plurality of hierarchical levels of design in graphical...
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US20090064075 |
SYSTEMS, METHODS AND COMPUTER PRODUCTS FOR SCHEMATIC EDITOR MULIT-WINDOW ENHANCEMENT OF HIERARCHICAL INTEGRATED CIRCUIT DESIGN
A method and apparatus for displaying hierarchical navigation and editing a plurality of hierarchical levels of design of an integrated circuit includes opening a main editor screen, displaying a...
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US20090055790 |
DESIGN STRUCTURE FOR ON CHIP SHIELDING STRUCTURE FOR INTEGRATED CIRCUITS OR DEVICES ON A SUBSTRATE
A design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure comprises: a conductive structure surrounding and...
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US20090037864 |
Methods for Designing Semiconductor Device with Dynamic Array Section
A method is provided for designing a semiconductor chip having one or more functionally interfaced dynamic array sections. A virtual grate is laid out for conductive features used to define a gate...
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US20090031273 |
METHOD FOR STACKED PATTERN DESIGN OF PRINTED CIRCUIT BOARD AND SYSTEM THEREOF
A method for designing stacked pattern of PCB utilizing genetic algorithm and the system thereof are disclosed. The method comprises the following steps: First of all, information data of stacked...
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US20090031272 |
CIRCUIT BOARD DESIGN TOOL AND METHODS
A design tool for printed circuit boards displays a graphical representation of a printed circuit board layout through a graphical user interface (GUI). Comments for particular components of the...
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US20090020850 |
SEMICONDUCTOR DESIGN APPARATUS, SEMICONDUCTOR CIRCUIT AND SEMICONDUCTOR DESIGN METHOD
According to an aspect of the present invention, there is provided a semiconductor design apparatus including: a determination section that determines a connection position of a capacitor to...
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US20090013298 |
Offset Fill
Techniques are described for increasing the density of structures in a layout circuit design, while reducing undesired total interconnect capacitance that might otherwise be created by the increase...
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US20090007046 |
Layout Method for Vertical Power Transistors Having a Variable Channel Width
The invention relates to a simulation and/or layout process for vertical power transistors as DMOS or IGBT with variable channel width and variable gate drain capacity which can be drawn and/or...
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