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US20120192133 LOGIC DESIGN VERIFICATION TECHNIQUES FOR LIVENESS CHECKING WITH RETIMING  
A technique for verification of a retimed logic design using liveness checking includes assigning a liveness gate to a liveness property for an original netlist and assigning a fairness gate to a...
US20110191740 ZONE-BASED OPTIMIZATION FRAMEWORK  
Some embodiments of the present invention provide techniques and systems for efficiently optimizing a circuit design for one or more multi-mode multi-corner (MCMM) scenarios. A system can select...
US20140282317 ARRIVAL EDGE USAGE IN TIMING ANALYSIS  
A logic design is analyzed using static timing analysis and timing edge tracking for various nets within the logic design. Crosstalk analysis is performed on the logic design to evaluate timing...
US20140282320 ANALYZING TIMING REQUIREMENTS OF A HIERARCHICAL INTEGRATED CIRCUIT DESIGN  
Logic gates in a child unit of a hierarchical integrated circuit design that are visible in an abstract model of the child unit of the hierarchical integrated circuit design are marked. A hide bit...
US20110055793 TIMING CLOSURE ON MULTIPLE SELECTIVE CORNERS IN A SINGLE STATISTICAL TIMING RUN  
An approach for covering multiple selective timing corners in a single statistical timing run is described. In one embodiment, a single statistical timing analysis is run on the full parameter...
US20110066989 METHOD AND SYSTEM TO AT LEAST PARTIALLY ISOLATE NETS  
A method to at least partially isolate a net of a circuit design is provided and includes testing a timing characteristic of a circuit design, identifying from a result of the testing a net of the...
US20130241597 INTEGRATED CIRCUIT WITH TIMING AWARE CLOCK-TREE AND METHOD FOR DESIGNING SUCH AN INTEGRATED CIRCUIT  
An integrated circuit includes a clock-tree with a plurality of clock buffers, a plurality of clocked storage elements, and a plurality of logic circuits. Each clocked storage element has a clock...
US20150026653 RELATIVE TIMING CHARACTERIZATION  
Technology for relative timing characterization enabling use of clocked electronic design automation (EDA) tool flows is disclosed. In an example, a method can include a EDA tool identifying a...
US20120047477 Method of Measuring the Impact of Clock Skew on Slack During a Statistical Static Timing Analysis  
Computing accurately and effectively the impact of clock skew on statistical slack in the presence of statistically variable timing quantities that accounts for both common path credit in the...
US20130227507 Recursive Hierarchical Static Timing Analysis  
A method for recursive hierarchical static timing analysis. The method includes accessing a lower-level netlist representing a lower-level block of a circuit design to be realized in physical...
US20110307850 RECURSIVE HIERARCHICAL STATIC TIMING ANALYSIS  
A method for recursive hierarchical static timing analysis. The method includes accessing a lower-level netlist representing a lower-level block of a circuit design to be realized in physical...
US20120284677 SLACK-BASED TIMING BUDGET APPORTIONMENT  
A slack-based timing budget apportionment methodology relies not only upon timing analysis-based determinations of slack in the units in an integrated circuit design, but also potential...
US20100223584 Logic Design Verification Techniques for Liveness Checking With Retiming  
A technique for verification of a retimed logic design using liveness checking includes assigning a liveness gate to a liveness property for an original netlist and assigning a fairness gate to a...
US20110131540 Path Preserving Design Partitioning With Redundancy  
Partitioning of a design allows STA to be performed in parallel on multiple, less demanding, and more available hardware resources. Therefore, runtime of STA can be significantly shortened....
US20140123089 MODELING MULTI-PATTERNING VARIABILITY WITH STATISTICAL TIMING  
Systems and methods for modeling multi-patterning variability with statistical timing analysis during IC fabrication are described. The method may be provided implemented in a computer...
US20110219344 Spatial Correlation-Based Estimation of Yield of Integrated Circuits  
Techniques for estimating yield of an integrated circuit design, such as a very-large-scale integration (VLSI) design, are provided. In one aspect, a method for determining a probability of...
US20110320992 BUFFER-AWARE ROUTING IN INTEGRATED CIRCUIT DESIGN  
A method, system, and computer usable program product for buffer-aware routing in integrated circuit design are provided in the illustrative embodiments. The design has cells, and the circuit...
US20150234959 METHOD AND APPARATUS USING FORMAL METHODS FOR CHECKING GENERATED-CLOCK TIMING DEFINITIONS  
A generated-clock checker compares timing definitions against a register transfer level description of the design using formal methods. The generated-clock checker derives generated-clock timing...
US20110140278 OPTICAL PROXIMITY CORRECTION AWARE INTEGRATED CIRCUIT DESIGN OPTIMIZATION  
An EDA method is implemented for modifying a layout file after place and route. The method includes storing a library of shape modifications for cells in the design library used for implementation...
US20130055174 METHOD FOR VERIFYING FUNCTIONAL EQUIVALENCE BETWEEN A REFERENCE IC DESIGN AND A MODIFIED VERSION OF THE REFERENCE IC DESIGN  
A method for verifying functional equivalence between a reference integrated circuit (IC) design and a modified version of the reference IC design includes simulating a reference IC design using a...
US20110093825 TECHNIQUES FOR ANALYSIS OF LOGIC DESIGNS WITH TRANSIENT LOGIC  
A technique for performing an analysis of a logic design includes detecting an initial transient behavior in a logic design embodied in a netlist. A duration of the initial transient behavior is...
US20110161902 Method and System for Synthesizing Relative Timing Constraints on an Integrated Circuit Design to Facilitate Timing Verification  
A method for synthesizing relative timing (RT) constraints on an integrated circuit design is disclosed. Initially, mulitple trace status tables are received, and each of the trace status tables...
US20130219352 LSI DESIGN METHOD  
Buffers on a clock tree are reduced, as long as there is enough set-up margin, in order to reduce power consumption in the clock tree. An FF group coupled to a partial tree, which is a part of the...
US20120124534 System and Method for Performing Static Timing Analysis in the Presence of Correlations Between Asserted Arrival Times  
A method of applying common path credit in a static timing analysis in the presence of correlations between asserted arrival times, comprising the steps of using a computer, identifying one or...
US20130007681 YIELD BASED FLOP HOLD TIME AND SETUP TIME DEFINITION  
Systems and method for defining a timing parameter for a circuit element based on process variation, including, determining a point of failure parameter associated with the timing parameter, the...
US20100313177 STATISTICAL ITERATIVE TIMING ANALYSIS OF CIRCUITS HAVING LATCHES AND/OR FEEDBACK LOOPS  
Statistical timing analysis methods for circuits having latches and feedback loops are described wherein the circuit yield, and/or the critical cycle mean (the largest cycle mean among all loops...
US20120266119 Delay Model Construction In The Presence Of Multiple Input Switching Events  
A method for constructing delay rules which include the effects of MIS simulations for static timing analysis with reduced cost. The present method includes constructing skew windows for applying...
US20130097567 CYCLE CUTTING WITH TIMING PATH ANALYSIS  
The timing cycles in a circuit design are identified and cut such that timing constraint paths in the circuit design are preserved. Timing cycles in the circuit design may be identified by...
US20110185335 DETERMINING AN ORDER FOR VISITING CIRCUIT BLOCKS IN A CIRCUIT DESIGN FOR FIXING DESIGN REQUIREMENT VIOLATIONS  
Some embodiments of the present invention provide techniques and systems for determining an order for visiting circuit blocks of a circuit design for fixing design requirement violations. Fixing...
US20120023466 IMPLEMENTING FORWARD TRACING TO REDUCE PESSIMISM IN STATIC TIMING OF LOGIC BLOCKS LAID OUT IN PARALLEL STRUCTURES ON AN INTEGRATED CIRCUIT CHIP  
A method, system and computer program product are provided for implementing forward tracing to reduce pessimism in static timing of logic blocks laid out in parallel structures on an integrated...
US20120254815 Method and System for Synthesizing Relative Timing Constraints on an Integrated Circuit Design to Facilitate Timing Verification  
A method for synthesizing relative timing (RT) constraints on an integrated circuit design is disclosed. Initially, multiple trace status tables are received, each containing a trace error...
US20140282321 SYSTEM AND METHOD FOR A HYBRID CLOCK DOMAIN CROSSING VERIFICATION  
A method of hybrid clock domain crossing (CDC) verification includes receiving a design or an integrated circuit (IC) design constraints. Static CDC verification is performed, including structural...
US20110191732 METHOD AND APPARATUS FOR DETERMINING A ROBUSTNESS METRIC FOR A CIRCUIT DESIGN  
Some embodiments provide techniques and systems for determining a change indicator for an endpoint, a pathgroup, a design, and/or a flow. The system can determine base critical path delays and...
US20110093830 Integrated Circuit Optimization Modeling Technology  
A design optimization method for a target circuit design specified by a machine-readable file, comprises providing a computer-implemented model as a function of a set of characteristics of circuit...
US20140040841 APPARATUS AND METHOD THEREOF FOR HYBRID TIMING EXCEPTION VERIFICATION OF AN INTEGRATED CIRCUIT DESIGN  
Timing Constraints are crucial to meet timing requirements of an Integrated Circuit (IC). Timing exceptions are specified so that certain paths of the design of the IC are not timed as they are...
US20120042294 APPARATUS AND METHOD THEREOF FOR HYBRID TIMING EXCEPTION VERIFICATION OF AN INTEGRATED CIRCUIT DESIGN  
Timing Constraints are crucial to meet timing requirements of an Integrated Circuit (IC). Timing exceptions are specified so that certain paths of the design of the IC are not timed as they are...
US20120151425 System and Method for Automatically Managing Clock Relationships in Integrated Circuit Designs  
Systems and methods for identifying and managing the relationships between clock domains in an integrated circuit design are disclosed. A computer-implemented method analyzes the behavioral...
US20130047127 METHOD AND APPARATUS FOR AUTOMATIC RELATIVE PLACEMENT GENERATION FOR CLOCK TREES  
Methods and apparatuses are disclosed for automatic relative placement of part of a clock tree in the course of generating a placed, routed, and optimized circuit design.
US20130227506 TIMING VERIFICATION METHOD FOR DETERMINISTIC AND STOCHASTIC NETWORKS AND CIRCUITS  
The timing verification method for deterministic and stochastic networks and circuits is a computerized method that includes a non-enumerative path length analysis algorithm for deterministic and...
US20110191730 ORDERING OF STATISTICAL CORRELATED QUANTITIES  
Solutions for ordering of statistical correlated quantities are disclosed. In one aspect, a method includes timing a plurality of paths in an integrated circuit to determine a set of timing...
US20110145771 Modeling for Soft Error Specification  
Soft error modeling of circuits. Soft error upset (SEU) specification and design information is received from a design entry. The SEU specification comprises expected SEU behavior of a node. A...
US20120017186 SPECIFYING CIRCUIT LEVEL CONNECTIVITY DURING CIRCUIT DESIGN SYNTHESIS  
Exemplary embodiments include a method for modifying a circuit synthesis flow having automated instructions, the method including receiving circuit design input for a circuit design, receiving...
US20110016442 Method of Performing Static Timing Analysis Considering Abstracted Cell's Interconnect Parasitics  
An abstraction model supporting multiple hierarchical levels is inputted into a generalized static timing analysis of a hierarchical IC chip design to analyze and optimize the design of circuits...
US20120311514 Decentralized Dynamically Scheduled Parallel Static Timing Analysis  
A method for performing a parallel static timing analysis in which multiple processes independently update a timing graph without requiring communication through a central coordinator module....
US20130246989 SYSTEM AND METHOD FOR METASTABILITY VERIFICATION OF CIRCUITS OF AN INTEGRATED CIRCUIT  
A system and methods for metastability verification of an integrated circuit design are provided. An IC design is received and the source-to-destination paths of the IC design are determined. For...
US20150248513 INTEGRATED CIRCUIT DESIGN TIMING PATH VERIFICATION TOOL  
An EDA tool for validating predefined timing paths having corresponding timing constraints in an integrated circuit (IC) design has a processor that performs a static-timing-analysis (STA) of the...
US20110252389 REDUCING CRITICAL CYCLE DELAY IN AN INTEGRATED CIRCUIT DESIGN THROUGH USE OF SEQUENTIAL SLACK  
A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in...
US20100318951 SYSTEM AND METHOD FOR DEVICE HISTORY BASED DELAY VARIATION ADJUSTMENT DURING STATIC TIMING ANALYSIS  
A system and method for the adjustment of history based delay variation during static timing analysis of an integrated circuit design. The method may include obtaining information through sources...
US20110167396 DESIGN PLACEMENT METHOD AND DEVICE THEREFOR  
An instantiation of a standard cell is placed at a location of a device design. The standard cell includes a designation identifying a sensitive feature of the standard cell. An instantiation of a...
US20130346932 INTELLIGENT TIMING ANALYSIS AND CONSTRAINT GENERATION GUI  
A system generally including a clock structure analysis tool, a static timing analysis tool and a waveform tool is disclosed. The clock structure analysis tool may be configured to generate a...

Matches 1 - 50 out of 319 1 2 3 4 5 6 7 >