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US20090319828 System, Method, and Device Including Built-In Self Tests for Communication Bus Device  
A method, device, and system including built-in self tests for a communication bus device is disclosed. In one form, a method of testing a device operable to be coupled to a communication port an...
US20090319840 SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD THEREOF  
A semiconductor memory device includes a nonvolatile memory functioning as a main memory unit, a volatile memory functioning as a buffer unit of the nonvolatile memory, a controller, an ECC buffer,...
US20090313511 SEMICONDUCTOR DEVICE TESTING  
A semiconductor device test circuit includes a data producing unit to produce first test data to be fed into a semiconductor device, and expected value data; a first data retaining unit to retain...
US20090307543 TRANSPORT SUBSYSTEM FOR AN MBIST CHAIN ARCHITECTURE  
An apparatus comprising a controller, a plurality of transport circuits and a plurality of memory-controlling circuits. The controller may be configured to (i) present one or more commands and (ii)...
US20090300441 ADDRESS CONTROLLING IN THE MBIST CHAIN ARCHITECTURE  
A memory collar includes a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a first control signal, a second control signal and a third control...
US20090300440 DATA CONTROLLING IN THE MBIST CHAIN ARCHITECTURE  
A memory collar including a first circuit and a second circuit. The first circuit may be configured to generate one or more data sequences in response to one or more test commands. The one or more...
US20090300445 METHOD AND SYSTEM FOR ALTERNATING BETWEEN PROGRAMS FOR EXECUTION BY CELLS OF AN INTEGRATED CIRCUIT  
A method and device for data processing in an integrated circuit having cells, the cells adapted for executing programs. A first program is run. In response to a waiting condition during which no...
US20090292949 SYSTEM AND METHOD OF MANAGING BIOS TEST ROUTNES  
A system and method of a basic input output system (BIOS) test system are disclosed. According to an aspect, a basic input output system (BIOS) test system can include a BIOS test manager...
US20090292963 Method and System for Testing an Electronic Circuit  
A method for testing an electronic circuit comprises selecting a first log interval, a first log start pattern, a first log end pattern, and a first subset range of LBIST patterns from a plurality...
US20090287971 METHOD AND APPARATUS FOR TESTING A RANDOM ACCESS MEMORY DEVICE  
A method and apparatus for testing a random access memory device is provided. One embodiment involves providing an interface between Logic Built in Self Test (LBIST) and Array Built in Self Test...
US20090271669 High-Speed Testing of Integrated Devices  
A method for allowing high-speed testability of a memory device having a core with memory cells for storing data, comprising: enabling a data signal having a first logical state or a second logical...
US20090235120 Systems and methods for testing a peripheral interfacing with a processor according to a MIPI protocol  
Systems and methods for testing a peripheral in accordance with a MIPI protocol are provided. A test system can test a peripheral by providing user-specified control over a test processor (which is...
US20090222652 EMBEDDED MEMORY PROTECTION  
One embodiment of the present application includes a microcontroller ( 30 ) that has an embedded memory ( 46 ), a programmable processor ( 32 ), and a test interface ( 34 ). The memory ( 46 ) is...
US20090217112 AC ABIST Diagnostic Method, Apparatus and Program Product  
A method for implementing at speed bit fail mapping of an embedded memory system having ABIST (Array Built In Self Testing), comprises using a high speed multiplied clock which is a multiple of an...
US20090210761 AC Scan Diagnostic Method and Apparatus Utilizing Functional Architecture Verification Patterns  
A method, apparatus and computer program product are provided for implementing AC scan diagnostic of delay and AC scan chain defects in an integrated circuit chip under test using Functional...
US20090187788 METHOD OF AUTOMATIC REGRESSION TESTING  
A method of automatic regression testing includes loading binary code representing a first version of a program, extracting a second version of the program embedded within the binary code of the...
US20090183044 Method and circuit for implementing enhanced LBIST testing of paths including arrays  
A method and circuit implement testing of a circuit path including a memory array and logic including Logic Built in Self Test (LBIST) diagnostics, and a design structure on which the subject...
US20090172487 Multiple pBIST Controllers  
A system on a single integrated circuit chip (SoC) includes a plurality of operational circuits to be tested. A plurality of programmable built-in self-test (pBIST) controllers is connected to...
US20090172483 ON-CHIP FAILURE ANALYSIS CIRCUIT AND ON-CHIP FAILURE ANALYSIS METHOD  
An on-chip failure analysis circuit for analyzing a memory comprises a memory in which data is stored, a built-in self test unit which tests the memory, an failure detection unit which detects an...
US20090158107 SYSTEM-ON-CHIP WITH MASTER/SLAVE DEBUG INTERFACE  
A System-on-Chip (SOC) integrated circuit (IC) debugging system includes a plurality of SOC ICs connected to a shared debug bus. One of the plurality of SOC ICs is a master SOC IC having a...
US20090144595 BUILT-IN SELF-TESTING (BIST) OF FIELD PROGRAMMABLE OBJECT ARRAYS  
A field programmable object array integrated circuit has built-in self-testing capability. The integrated circuit comprises an array of programmable objects, a plurality of interfaces, and a...
US20090083598 METHOD FOR MONITORING AND ADJUSTING CIRCUIT PERFORMANCE  
A method for testing an integrated circuit implemented in an electronic system. The method includes placing an integrated circuit (or portion thereof) that is implemented in an operational system...
US20090083592 SEMICONDCUTOR DEVICE, MEMORY SYSTEM AND CONTROL METHOD OF THE SEMICONDUCTOR DEVICE  
A semiconductor device including a logic circuit and a test circuit is provided which comprises: a logic signal terminal that supplies a signal to the logic circuit; a latch circuit that latches a...
US20090063921 Staggered LBIST Clock Sequence for Noise (di/dt) Amelioration  
A method, device and system for performing on-chip testing are presented. In particular, the present invention provides a method, device and system for reducing noise due to large changes in...
US20090063917 SEMICONDUCTOR INTEGRATED CIRCUIT  
A semiconductor integrated circuit includes: a memory collars including: a memory cell; a fetch register that is configured to fetch data as a first fetch data; a comparing unit that is configured...
US20090024885 SEMICONDUCTOR INTEGRATED CIRCUIT AND TEST SYSTEM THEREOF  
A semiconductor integrated circuit has a memory collar including a memory cell configured to store a written data pattern and read and output the data pattern, and a register configured to store a...
US20090024889 INTEGRATED CIRCUIT HAVING BUILT-IN SELF-TEST FEATURES  
An integrated circuit and a method of built-in self test in the integrated circuit employ an offset control node and offset capabilities with the integrated circuit in order to communicate and...
US20090019329 Serial scan chain control within an integrated circuit  
An integrated circuit 2 includes a plurality of circuit blocks 38, 40, 44 each having an associated serial scan chain loop 32, 34, 36 which extends from a converter 10 , to the circuit block...
US20090019331 Integrated circuit for a data transmission system and receiving device of a data transmission system  
The invention relates to an integrated circuit for a data transmission system comprising a) a plurality of functional units, b) a TAP controller, according to IEEE 1149, having a JTAG interface,...
US20090013228 BIST DDR MEMORY INTERFACE CIRCUIT AND METHOD FOR TESTING THE SAME  
An apparatus and method for self-testing a DDR memory interface are disclosed. In one aspect, a built-in-self-test (BIST) memory interface circuit comprises a signal multiplier for receiving a...
US20080307261 ACTIVATING A DESIGN TEST MODE IN A GRAPHICS CARD HAVING MULTIPLE EXECUTION UNITS  
Provided are a method and system for activating a design test mode in a graphics card having multiple execution units. A design test mode is activated in a graphics module comprising multiple...
US20080301511 INTEGRATED CIRCUIT WITH CONTINUOUS TESTING OF REPETITIVE FUNCTIONAL BLOCKS  
A method of continuous testing of repetitive functional blocks provided on an integrated circuit (IC) which includes selecting one of the repetitive functional blocks at a time for testing,...
US20080282119 MEMORY DEVICE AND BUILT IN SELF-TEST METHOD OF THE SAME  
A memory device including, a nonvolatile memory which stores a step item, a parameter start address, and a parameter which has an address corresponding to the parameter start address and defines...
US20080270836 STATE DISCOVERY AUTOMATON FOR DYNAMIC WEB APPLICATIONS  
An automaton that detects possible states and transitions that can possibly exist in a web based application is provided. The automaton may comprise a plugin system, an HTTP processor, an...
US20080263414 SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM  
The test design cost of a circuit capable of accessing an external memory is reduced. There is included a built-in self-test circuit for use in testing an external memory separately from a memory...
US20080256407 PROCESS AND SYSTEM FOR THE VERIFICATION OF CORRECT FUNCTIONING OF AN ON-CHIP MEMORY  
A method is for making an integrated circuit with built-in self-test. The method includes forming at least one nonvolatile read only memory (ROM) to store ROM code and forming a logic self-test...
US20080235547 SELF-TEST OUTPUT FOR HIGH-DENSITY BIST  
A method, apparatus and system of a self-test output for high density BIST are disclosed. In one embodiment, an integrated circuit includes one or more memories, a BIST controller coupled to the...
US20080222464 Structure for System for and Method of Performing High Speed Memory Diagnostics Via Built-In-Self-Test  
A design structure for a system for and method of performing high speed memory diagnostics via built-in-self-test (BIST) is disclosed. In particular, a test system includes a tester for testing an...
US20080215937 REMOTE BIST FOR HIGH SPEED TEST AND REDUNDANCY CALCULATION  
Disclosed in a hybrid built-in self test (BIST) architecture for embedded memory arrays that segments BIST functionality into remote lower-speed executable instructions and local higher-speed...
US20080209293 PROBING SYSTEM FOR INTEGRATED CIRCUIT DEVICES  
A probing system for integrated circuit device, which transmits testing data/signal between an automatic test equipment (ATE) and an integrated circuit device, is disclosed. The probing system...
US20080195901 OP-CODE BASED BUILT-IN-SELF-TEST  
A built-in-self-test (BIST) system for testing a memory that includes a scheduler module that generates a first test algorithm based on a set of operational codes. Each operational code defines a...
US20080178053 HYBRID BUILT-IN SELF TEST (BIST) ARCHITECTURE FOR EMBEDDED MEMORY ARRAYS AND AN ASSOCIATED METHOD  
Disclosed are embodiments of a built-in self-test (BIST) architecture that incorporates a standalone controller that operates at a lower frequency to remotely perform test functions common to a...
US20080155363 BIST CIRCUIT DEVICE AND SELF TEST METHOD THEREOF  
A BIST circuit device includes a test memory, a test result storage memory having the capacity equal to or larger than the capacity of the test memory, and a control circuit which performs a test...
US20080148119 Apparatus for Built-in Speed Grading and Method for Generating Desired Frequency for the Same  
A method for Built-In Speed Grading (BISG) comprises a Circuit Under Test (CUT) with Built-In Self-Test (BIST) circuitry, an All-Digital Phase-Locked Loop (ADPLL), and a BISG, to automatically...
US20080148114 REDUNDANCY PROGRAMMING FOR A MEMORY DEVICE  
A method for implementing redundancy programming in a memory macro of an integrated circuit chip. It is assumed that all fails are row fails until determined to be bitline fails, test patterns are...
US20080141089 Semiconductor Integrated Circuit and System Lsi  
In a semiconductor integrated circuit 11, there is constructed a test expected value programming circuit 100 having an input/input-output pad 103 for retrieving a ground/power-source signal ...
US20080133992 METHOD, APPARATUS AND COMPUTER PROGRAM PRODUCT FOR IMPLEMENTING SCAN-CHAIN-SPECIFIC CONTROL SIGNALS AS PART OF A SCAN CHAIN  
A method, apparatus and computer program product are provided for implementing scan-chain-specific control signals as an integral part of a scan chain. A scan input vector including scan data input...
US20080126863 Testing DRAM Chips with a PC Motherboard Attached to a Chip Handler by a Solder-Side Adaptor Board with an Advanced-Memory Buffer (AMB)  
Memory chips are tested by insertion into a chip test socket on a test adapter board that is mounted to the reverse or solder-side of a personal computer motherboard. A memory module socket is...
US20080126900 Array delete mechanisms for shipping a microprocessor with defective arrays  
Detecting and correcting errors in arrays after ABIST testing, after ABIST testing, detected errors are faults are isolated by blowing a fuse.
US20080125990 BUILT-IN SELF TEST CIRCUIT FOR ANALOG-TO-DIGITAL CONVERTER AND PHASE LOCK LOOP AND THE TESTING METHODS THEREOF  
A BIST circuit for testing both an analog-to-digital converter and a phase lock loop includes a controllable delay circuit, a NAND gate, a dividing circuit, a NOR gate and a charge/discharge...
Matches 1 - 50 out of 59 1 2 >