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US20120036416 LIST VITERBI DECODING OF TAIL BITING CONVOLUTIONAL CODES  
A low complexity List Viterbi algorithm (LVA) for decoding tail biting convolutional codes (TBCCs) has lower complexity than a solution of running the LVA algorithm for all states. In one aspect,...
US20130238962 SYSTEMS AND METHODS FOR NETWORK CODING USING CONVOLUTIONAL CODES  
A network coding method includes receiving a plurality of message packets each having a packet length. Encoding the plurality of message packets by applying a convolutional code across symbols in...
US20140143641 ITERATIVE DECODER SYSTEMS AND METHODS  
Systems and methods are provided for improved designs and performance for iterative decoder systems. In some embodiments, the iterative decoder may be decoupled from FIR samples through an FIR...
US20110283170 Viterbi Decoder and Writing and Reading Method  
A Viterbi decoder includes a survival memory unit, for storing a plurality of survivor metric into a writing column of a writing bank of a plurality of banks in alternating intervals of a clock...
US20110138260 LDPC coding process with incremental redundancy  
The invention relates to a coding method with incremental redundancy in which it is determined (620) whether to carry out the coding of a sequence of information symbols using a first code (C), of...
US20110231741 SYSTEM AND METHOD FOR VITERBI DECODING USING APPLICATION SPECIFIC EXTENSIONS  
A system and method for Viterbi decoding utilizes a general purpose processor with application specific extensions to perform Viterbi decoding operations specified in a Viterbi decoding algorithm...
US20070183539 Viterbi decoding circuit and wireless device  
A setting register is provided in which parameters including a code rate, a constraint length, and a generator polynomial are changeably set according to a type of wireless communication standard,...
US20140129908 VITERBI BUTTERFLY OPERATIONS  
A decoding system suitable for Viterbi decoding includes a decoder that includes a state metrics array, a butterfly unit, and a constraint length multiplexer. The state metrics array includes...
US20090232256 ITERATIVE DECODING FOR LAYER CODED OFDM COMMUNICATION SYSTEMS  
A modified classical Viterbi decoder which can take extrinsic information and output hard decisions. A modified Viterbi decoder is provided comprising a branch metric unit, the unit having a...
US20100034325 LOW-POWER PREDECODING BASED VITERBI DECODING  
In at least some disclosed embodiments, a system includes a Viterbi decoder and predecoding logic coupled to the Viterbi decoder. The predecoding logic decodes encoded data. The system further...
US20110161787 POWER-REDUCED PRELIMINARY DECODED BITS IN VITERBI DECODERS  
Various embodiments relate to a storage unit and a related method in a Viterbi decoder for decoding a binary convolutional code with power efficiency. A storage unit for storing survivor paths may...
US20070101245 Method for reducing the computational complexity of Viterbi decoder  
A method for reducing the computational complexity of a Viterbi decoder, which is suitable for all code rates of a convolutional code applied by the Viterbi decoder. The method dramatically...
US20090070658 DEFECT SENSING VITERBI BASED DETECTOR  
During decoding using a Viterbi based detector, erasures are detected when surviving paths do not merge in an associated decoding window.
US20090172504 MEMORY ARCHITECTURE FOR VITERBI DECODER AND OPERATING METHOD THEREFOR  
The Viterbi decoder is an essential module in a communication system, in which the power and the decoding latency are restricted. In the present invention, a power efficient low latency survivor...
US20120042229 MULTI-STANDARD VITERBI PROCESSOR  
Various embodiments relate to a multi-standard Viterbi decoder. Based on programmable values for constraint length, generator polynomials, and code rate, the multi-standard Viterbi decoder may...
US20110060972 DECODING METHOD FOR TAIL-BITING CONVOLUTIONAL CODES USING A SEARCH DEPTH VITERBI ALGORITHM  
A method for decoding tail-biting convolutional codes. The method includes initializing a correction depth, selecting a first starting state from a set of encoding states, and initializing a...
US20060015799 Proxy-based error tracking for real-time video transmission in mobile environments  
This invention provides an efficient method of error tracking which quickly recovers the error packet of data. A side information is sent along with a normal video stream that can be used by an...
US20070245208 Erasures assisted block code decoder and related method  
An erasures assisted block code decoder and related method are provided. The erasures assisted block code decoder comprises a first block decoder, an erasures processor, and a second block code...
US20080162617 High-speed radix-4 butterfly module and method of performing biterbi decoding using the same  
A high-speed radix-4 butterfly module and the method of performing Viterbi decoding using the same. The high-speed radix-4 butterfly module includes first to fourth add-compare-select (ACS)...
US20090238311 Reverse serial list Viterbi decoding to improve frame error rate performance  
A convolutionally encoded frame to be decoded includes a first portion of bits having additional error protection and another portion without additional error protection. The decoding of the frame...
US20100185923 DECODING OF RECURSIVE CONVOLUTIONAL CODES BY MEANS OF A DECODER FOR NON-RECURSIVE CONVOLUTIONAL CODES  
Embodiments of the invention provide a decoder arrangement (400), wherein a decoder (420) which is adapted to decode a bitstream which has been encoded with a non-recursive convolutional encoder...
US20090022250 Conditionally Input Saturated Viterbi Detector  
Various embodiments of the present invention provide systems and methods for decoding encoded information. For example, a decoder including a branch metric calculator that conditionally calculates...
US20120137198 LOW COMPLEXITY DECODING ALGORITHM FOR TAIL-BITING CONVOLUTIONAL CODES  
A method for decoding tail-biting convolutional codes. The method includes initializing a correction depth, selecting a first starting state from a set of encoding states, and initializing a...
US20080192865 Addressing Strategy for Viterbi Metric Computation  
The present invention relates to an addressing architecture for parallel processing of recursive data. A basic idea of the present invention is to store a calculated new path metric at the memory...
US20090089648 LOW POWER VITERBI DECODER USING SCARCE STATE TRANSITION AND PATH PRUNING  
Low power Viterbi decoder techniques using Scarce State Transition (SST) and path pruning and related methods and systems are provided, which facilitate practical implementations that reduce the...
US20070266303 VITERBI DECODING APPARATUS AND TECHNIQUES  
Viterbi decoding techniques that include multi-stage Viterbi decoding of encoded signals. Such techniques include radix-4 two stage decoding. The encoded signals may include soft decision signals....
US20130185615 SOFT OUTPUT VITERBI DETECTOR WITH ERROR EVENT OUTPUT  
A first sequence of states associated with a surviving path and a second sequence of states associated with a non-surviving path are determined. A possible error event is determined based at least...
US20080240278 JOINT DECODING OF ISI (INTER-SYMBOL INTERFERENCE) CHANNEL AND MODULATION CODES  
Joint decoding of ISI (Inter-Symbol Interference) channel and modulation codes. A means is presented by which a single, combined ISI and modulation decoding module is operable to process a signal...
US20070033508 Interative stripewise trellis-based symbol detection method and device for multi-dimensional recording systems  
When processing a two dimensional data area it is known to be advantageous to divide the two dimensional are into stripes and process each stripe using a stripe-wise detector. The stripe being...
US20070111718 Power management system for SCA based software defined radio and related method  
A software defined radio includes a radio circuit powered by a battery and formed as a pair of radio subsystems having radio components that draw power from the battery. An executable radio...
US20090125794 ACS UNIT OF A VITERBI DECODER AND METHOD FOR CALCULATING A BIT ERROR RATE BEFORE A VITERBI DECODER  
An ACS unit of a Viterbi decoder and a method for calculating the bit error rate (BER) before Viterbi decoder are provided. The ACS unit includes a state calculator and a BER calculator. The state...
US20090317094 Maximum Likelihood Sequence Estimation in Optical Fibre Communication Systems  
A method of and a receiver(20) for detection of a received signal in an optical fibre communication system using Viterbi algorithm methodology in which branch metrics are obtained using...
US20080115035 Post-viterbi error correction method and apparatus  
In an error correction method, a codeword is transmitted through a noisy communication channel and detected by a receiving device. An error detection code is then applied to the detected codeword...
US20070277081 Dynamic power adjusting device for viterbi decoder  
A dynamic power adjusting device for a Viterbi decoder is disclosed. The device includes a processing unit for receiving a plurality of data to be decoded, detecting whether the data to be decoded...
US20070067704 Deinterleaver and dual-viterbi decoder architecture  
Pairs of parallel Viterbi decoders use windowed block data for decoding data at rates above 320 Mbps. Memory banks of the deinterleavers feeding the decoders operate such that some are receiving...
US20070234190 Viterbi Decoding Apparatus and Viterbi Decoding Method  
In a Viterbi decoding apparatus, deterioration in error correcting capability before and after a terminated code is controlled. A termination timing detection unit (103) detects a termination...
US20100299583 OPTIMIZED VITERBI DECODER AND GNSS RECEIVER  
A Viterbi decoder which is based on a special instruction set implemented in the processor, enabling it to handle the Viterbi processing with a much lower CPU loading without significantly...
US20090193321 VITERBI DECODER AND VITERBI DECODING METHOD  
A Viterbi decoder and a Viterbi decoding method are provided for simplifying hardware and increasing an operation speed by using a decision feedback unit selecting one of at least two levels based...
US20070106926 Viterbi decoding method and apparatus for high speed data transmissions  
Disclosed are a Viterbi decoding method and apparatus for high speed data transmissions. Branch metric is used with data inputted from a Viterbi decoder used in a communication system, and, when...
US20090013234 DATA STORAGE WITH AN OUTER BLOCK CODE AND A STREAM-BASED INNER CODE  
Apparatus and methods store stream-based error recovery data for a memory array, such as a NAND flash array. Conventionally, data is block coded per industry specification and stored in the memory...
US20090319875 Path Metric Difference Computation Unit For Computing Path Differences Through A Multiple-Step Trellis  
A path metric difference computation unit is disclosed for computing path differences through a multiple-step trellis. The disclosed path metric difference computation unit computes differences...
US20100185925 Differential Locally Updating Viterbi Decoder  
The present invention relates to differential, locally updating Viterbi decoder characterized in that it contains connection management block (802, 810, 812) which enables decoding a bit per cycle...
US20050071734 Methods and systems for Viterbi decoding  
An execution unit and a new set of instructions for performing Viterbi decoding are provided. The instructions can be built into an execution unit which executes other instructions, or in their...
US20100269026 ERROR PATTERN GENERATION FOR TRELLIS-BASED DETECTION AND/OR DECODING  
The disclosed technology provides systems and methods for identifying potential error locations, patterns, and likelihood metrics in connection with trellis-based detection/decoding. In one aspect...
US20110083063 Continuous Parallel Viterbi Decoder  
A continuous parallel Viterbi decoder comprises input means for computing Trellis paths from an input bitstream encoded with a convolutional code; output means for backtracking the Trellis paths...
US20150074501 Cascaded Viterbi Bitstream Generator  
A bitstream generator includes at least first and second bitstream generator stages connected in a cascaded arrangement. The first bitstream generator stage includes a first adder which receives...
US20070220408 Decoding a Concatenated Convolutional-Encoded and Block Encoded Signal  
Encoded symbols of a concatenated convolutional-encoded and block encoded signal are presented to a conventional first stage of a concatenated decoder, comprising in sequence a soft metric...
US20110307767 METHOD AND APPARATUS FOR SIGNAL-TO-NOISE RATIO ESTIMATION IN CONVOLUTIONAL CODES (VITERBI) DECODER  
A method of estimating signal-to-noise ratio in a Viterbi decoder comprising: setting a threshold SNR value; determining a dependence on SNR of the average decoding path length; filling branch...
US20100058152 DECODING APPARATUS AND METHOD  
A-decoding-apparatus includes first-equalization-unit configured to obtain an-equalized-bit-string subjected to hard-decision by equalizing the-input-signal, and to obtain reliability-value-data...
US20100287451 Incremental generation of polynomials for decoding reed-solomon codes  
An error locator polynomial is incrementally generated by flipping a bit pattern Yi at a symbol Xi an initial dataword to obtain a first test error pattern. A bit pattern Yj at a symbol Xj within...

Matches 1 - 50 out of 115 1 2 3 >