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US20140032997 QPP INTERLEAVER/DE-INTERLEAVER FOR TURBO CODES  
A quadratic permutation polynomial (QPP) interleaver is described for turbo coding and decoding. The QPP interleaver has the form: Π(n)=f1n−fnn2 mod K, where the QPP coefficients f1 and f2 are...
US20110072334 SYSTEMATIC ENCODER WITH ARBITRARY PARITY POSITIONS  
An encoder structure for an error correcting code with arbitrary parity positions is presented. The invention is effective for all error correcting codes whose parity check matrix is of the...
US20130086456 System and Method for Determining Quasi-Cyclic Low-Density Parity-Check Codes Having High Girth  
A system and a method determine a quasi-cyclic (QC) low-density parity-check (LDPC) code corresponding to a protograph and having a predetermined girth. At least several elements of the...
US20100332956 POLYNOMIAL DIVISION  
Systems and methods to perform polynomial division are disclosed. In a particular embodiment, the method includes receiving a codeword and storing a portion of the received codeword at a register....
US20140059409 SYSTEM AND METHOD HAVING OPTIMAL, SYSTEMATIC q-Ary CODES FOR CORRECTING ALL ASYMMETRIC AND SYMMETRIC ERRORS OF LIMITED MAGNITUDE  
A computer-implemented method and computer program product comprising optimal, systematic q-ary codes for correcting all asymmetric and symmetric errors of limited magnitude are provided.
US20100299579 Methods and Systems for Error-Correction in Convolutional and Systematic Convolutional Decoders in Galois Configuration  
Convolutional coders having an n-state with n≧2 Linear Feedback Shift Registers (LFSR) in Galois configuration with k shift register elements with k>1 are provided. Corresponding decoders are also...
US20120185755 METHOD FOR PERFORMING SOFT DECISION DECODING OF EUCLIDEAN SPACE REED-MULLER CODES  
Soft decision decoding of a codeword of a Reed-Muller (RM) code by selecting an optimal decomposition variable i using a likelihood calculation. A code RM(r, m) is expressed as {(u, uv)|uεRM(r,...
US20130346833 PROCESSING ELEMENTARY CHECK NODES OF AN ITERATIVE ED TRANSMITTER APPAR  
Embodiments of the present disclosure describe devices, apparatus, methods, computer-readable media and system configurations for processing elementary check nodes associated with an iterative...
US20110004811 Encoding/decoding apparatus and method  
An encoder and a decoder employ an encoding scheme corresponding to a parity check matrix which is derivable from a bipartite protograph formed of variable nodes and check nodes, with each...
US20120254702 ERROR CORRECTION APPARATUS AND ERROR CORRECTION METHOD  
A plurality error correction circuits connected with series includes a calculator circuit corrects the codeword when the determination results of a determining circuit indicate that the error...
US20110320917 METHOD OF DETERMINING A COORDINATE VALUE WITH RESPECT TO PATTERNS PRINTED ON A DOCUMENT  
A method is disclosed of determining a coordinate value with respect to patterns printed on a document. Each pattern represents a sequence, with each sequence consisting of a repeating codeword of...
US20130254635 Chien Search Using Multiple Basis Representation  
A method for decoding an Error Correction Code (ECC) includes accepting coefficients, including at least first and second coefficients, of an Error Locator Polynomial (ELP) that is defined over a...
US20100332955 CHIEN SEARCH USING MULTIPLE BASIS REPRESENTATION  
A method for decoding an Error Correction Code (ECC) includes accepting coefficients, including at least first and second coefficients, of an Error Locator Polynomial (ELP) that is defined over a...
US20130073928 POWER-OPTIMIZED DECODING OF LINEAR CODES  
A method includes accepting an input code word, which was produced by encoding data with an Error Correction Code (ECC), for decoding by a hardware-implemented ECC decoder. The input code word is...
US20080065967 System for controlling high-speed bidirectional communication  
A system for controlling high-speed bidirectional communication includes a slave device such as a memory device, for example, coupled to a master device such as a memory controller, for example....
US20120192040 ENCODING DEVICE FOR ERROR CORRECTION, ENCODING METHOD FOR ERROR CORRECTION AND ENCODING PROGRAM FOR ERROR CORRECTION  
The present invention aims at providing an encoding device for error correction, encoding method for error correction and encoding program for error correction wherein countermeasures against...
US20090119568 Single CRC polynomial for both turbo code block CRC and transport block CRC  
Single CRC polynomial for both turbo code block CRC and transport block CRC. Rather than employing multiple and different generation polynomials for generating CRC fields for different levels...
US20110219287 REMOTE PRESENTATION OVER LOSSY TRANSPORT WITH FORWARD ERROR CORRECTION  
In various embodiments, methods and systems are disclosed for integrating a remote presentation protocol with a datagram based transport. In one embodiment, an integrated protocol is configured to...
US20140237325 STAIRCASE FORWARD ERROR CORRECTION CODING  
In staircase forward error correction coding, a stream of data symbols are mapped to data symbol positions in a sequence of two-dimensional symbol blocks Bi, i a positive integer. Each of the...
US20100174968 HEIRARCHICAL ERASURE CODING  
Arrangements are provided for efficient erasure coding of files to be distributed and later retrieved from a peer-to-peer network, where such files are broken up into many fragments and stored at...
US20080148129 Error detection and correction using error pattern correcting codes  
In general, the disclosure describes techniques for detecting and correcting single or multiple occurrences of data error patterns. This disclosure discusses the generation and application of...
US20080168334 Low Complexity LDPC Encoding Algorithm  
A method of encoding a binary source message u, by calculating x:=Au, calculating y:=B″x, resolving the equation Dp=y for p, and incorporating u and p to produce an encoded binary message v, where...
US20100031125 Tail-biting turbo coding to accommodate any information and/or interleaver block size  
Tail-biting turbo coding to accommodate any information and/or interleaver block size. A means is presented by which the beginning and ending state of a turbo encoder can be made the same using a...
US20080092020 Determining message residue using a set of polynomials  
A method is described for use in determining a residue of a message. The method includes loading at least a portion of each of a set of polynomials derived from a first polynomial, g(x), and...
US20150007000 Additional Error Correction Apparatus and Method  
An encoder provides (2t−1) redundant symbols in a sequence of n coded symbols, and a decoder corrects up to t erroneous symbols in the sequence of n coded symbols corrupted by a plurality of...
US20070150795 Performing a cyclic redundancy checksum operation responsive to a user-level instruction  
In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a...
US20130073925 ELECTRONIC DEVICE COMPRISING ERROR CORRECTION CODING DEVICE AND ELECTRONIC DEVICE COMPRISING ERROR CORRECTION DECODING DEVICE  
An electronic device comprises an error correction coding device. The error correction coding device comprises a parity code generator. This generator is a circuit for computing a remainder...
US20080115034 QPP Interleaver/De-Interleaver for Turbo Codes  
A quadratic permutation polynomial (QPP) interleaver is described for turbo coding and decoding. The QPP interleaver has the form: Π(n)=f1n+f2n2 mod K, where the QPP coefficients f1 and f2. are...
US20150188572 Variable Speed Chien Search Architecture  
Examples are disclosed for using or designing Chien search circuitry to locate errors for error correction code (ECC) encoded data. In some examples, an error locator polynomial (ELP) may be...
US20100185923 DECODING OF RECURSIVE CONVOLUTIONAL CODES BY MEANS OF A DECODER FOR NON-RECURSIVE CONVOLUTIONAL CODES  
Embodiments of the invention provide a decoder arrangement (400), wherein a decoder (420) which is adapted to decode a bitstream which has been encoded with a non-recursive convolutional encoder...
US20090222708 ERROR CORRECTING DEVICE AND ERROR CORRECTING METHOD  
An error correcting device for correcting erroneous data included in data read out from a nonvolatile memory includes a determining unit that determines whether the data read out from the...
US20100031127 SCHEME FOR ERASURE LOCATOR POLYNOMIAL CALCULATION IN ERROR-AND-ERASURE DECODER  
A method to generate an erasure locator polynomial in an error-and-erasure decode. The method generally includes the steps of (A) storing current values in multiple registers at a current moment,...
US20090282320 ITERATIVE DECODER WITH STOPPING CRITERION GENERATED FROM ERROR LOCATION POLYNOMIAL  
A decoder for error correction an encoded message, such as one encoded by a turbo encoder, with reduced iterations due to an improved stopping criterion. The decoder includes an error correction...
US20070118790 Apparatus and method for stopping iterative decoding in a mobile communication system  
An apparatus and method are provided for stopping iterative decoding in a channel decoder of a mobile communication system. Constituent decoding of received signals is performed and decoded...
US20110107188 SYSTEM AND METHOD OF DECODING DATA  
A decoder is disclosed that can reduce power consumption at different stages of a decoding process. At a first stage where the decoder calculates residual values, the decoder can reduce power...
US20090031196 Error-correcting method used for decoding data transmissions  
An error-correcting method used for decoding of data transmissions is disclosed. The error-correcting method is used for data with an error-correcting part and comprises: providing a multinomial...
US20130031446 CODING DEVICE, ERROR-CORRECTION CODE CONFIGURATION METHOD, AND PROGRAM THEREOF  
A coding device includes: an inspection matrix generating module that generates a block inspection matrix; and a coding module that generates and outputs a code word from an input message by the...
US20100169747 OPTIMUM DISTANCE SPECTRUM FEEDFORWARD LOW RATE TAIL-BITING CONVOLUTIONAL CODES  
Method and apparatus for generating a set of generator polynomials for use as a tail biting convolutional code to operate on data transmitted over a channel comprises: (0) specifying a constraint...
US20080134008 Parallel LDPC Decoder  
An LDPC decoder that implements an iterative message-passing algorithm, where the improvement includes a pipeline architecture such that the decoder accumulates results for row operations during...
US20070300135 Error Correction Encoding Apparatus and Error Correction Encoding Method Used Therein  
An error correction encoding apparatus wherein the apparatus structure is simple; an iterative decoding is used to achieve a decoding with a close-to-optimum precision; and a simple mathematical...
US20090132895 ERROR CORRECTING CODES FOR RANK MODULATION  
We investigate error-correcting codes for a novel storage technology, which we call the rank-modulation scheme. In this scheme, a set of n cells stores information in the permutation induced by...
US20070130490 Information protection using properties of a printed electronic circuit  
Apparatus and methods for manufacturing and reading the apparatus is disclosed. The apparatus includes: a storage medium (610) comprising a first material; and a printed electronic circuit (104)...
US20100251079 METHOD AND DEVICE FOR INFORMATION BLOCK CODING AND SYNCHRONIZATION DETECTING  
A method and a device for information block coding and synchronization detecting are provided. Information block coding and synchronization detecting are preformed according to a synchronization...
US20070150797 Partial iterative detection and decoding apparatus and method in MIMO system  
A partial iterative detection and decoding apparatus in a Multiple Input Multiple Output (MIMO) system includes a detector for detecting signals received through at least one receive antenna to...
US20080282132 Error Correcting Code  
A system 100 for protecting a codeword u against an error in at least one <7-ary symbol, where q is an rΛ of two, r≧1 (q=T). The code word u 300 includes information symbols 310 u[0], . . . ,...
US20080259891 MULTIPLE PACKET SOURCE ACKNOWLEDGEMENT  
A multi-bit acknowledgement word (44) is prepared by a first communications station 22 (such as a base station) for separately acknowledging the success or failure of data packets received over...
US20150039975 ERROR CORRECTION DEVICE AND ERROR CORRECTION METHOD  
According to one embodiment, an error correction device includes a syndrome processing unit, a generation unit, and a search processing unit. The syndrome processing unit generates a syndrome...
US20110145683 Instruction-set architecture for programmable cyclic redundancy check (CRC) computations  
A method and apparatus to perform Cyclic Redundancy Check (CRC) operations on a data block using a plurality of different n-bit polynomials is provided. A flexible CRC instruction performs a CRC...
US20060195768 Techniques for performing reduced complexity galois field arithmetic for correcting errors  
Techniques are provided for performing Galois field arithmetic to detect errors in digital data stored on disks. Two 12-bit numbers or two 10-bit numbers are multiplied together in Galois field...
US20100058146 CHIEN-SEARCH SYSTEM EMPLOYING A CLOCK-GATING SCHEME TO SAVE POWER FOR ERROR CORRECTION DECODER AND OTHER APPLICATIONS  
Chien search apparatus operative to evaluate an error locator polynomial having a known rank and including a sequence of terms for each element in a finite field whose elements correspond...

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