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US20140143634 NON-REGULAR PARITY DISTRIBUTION DETECTION VIA METADATA TAG  
This can relate to non-regular parity distribution of a non-volatile memory (“NVM”), such as flash memory, and detection of the non-regular parity via a metadata tag. For example, each codeword of...
US20130191702 FORWARD ERROR CORRECTION WITH CONFIGURABLE LATENCY  
A method of performing forward error correction with configurable latency, where a configurable latency algorithm evaluates a target Bit Error Rate (BER) against an actual BER and adjusts the size...
US20150205670 METHOD AND SYSTEM FOR SERVICE-AWARE PARITY PLACEMENT IN A STORAGE SYSTEM  
A method and system for service-aware parity placement in a storage system, including after receiving the service notification specifying a target SD: writing a RAID stripe to the persistent...
US20140026014 SOFT DECODING FOR QUANTIZIED CHANNEL  
Systems, methods, and other embodiments associated with soft decoding for a quantized channel are described. According to one embodiment, a method includes repetitively controlling the soft...
US20150212882 PHYSICAL PAGE, LOGICAL PAGE, AND CODEWORD CORRESPONDENCE  
The present disclosure includes apparatuses and methods for physical page, logical page, and codeword correspondence. A number of methods include error coding a number of logical pages of data as...
US20150154070 MIXED GRANULARITY HIGHER-LEVEL REDUNDANCY FOR NON-VOLATILE MEMORY  
Mixed-granularity higher-level redundancy for NVM provides improved higher-level redundancy operation with better error recovery and/or reduced redundancy information overhead. For example, pages...
US20070113156 Information processing method and apparatus, recording medium, and program  
An information processing method includes generating a state transition diagram based on state transition information; displaying the state transition diagram; manipulating the displayed state...
US20080098280 N-dimensional iterative ECC method and apparatus with combined erasure - error information and re-read  
In an iterative error correction method and apparatus for correcting errors in digital data read from a storage medium, re-reads are combined with the error correction procedure in a single error...
US20150186214 ASSIGNING A DISPERSED STORAGE NETWORK ADDRESS RANGE IN A MAINTENANCE FREE STORAGE CONTAINER  
A maintenance free storage container includes a container housing, storage servers, and a container controller. The container controller includes a processing module that is operable to maintain...
US20150199235 Optimizing and Enhancing Performance for Parity Based Storage  
A mechanism is provided for optimizing and enhancing performance for parity based storage, particularly redundant array of independent disk (RAID) storage. The mechanism optimizes a repetitive...
US20140026015 SYSTEMS AND METHODS FOR EFFICIENT LOW DENSITY PARITY CHECK (LDPC) DECODING  
A method for low density parity code decoding according to one embodiment includes sequentially processing groups of variable node (vim& values associated with a codeword using a plurality of...
US20140380126 ERASURE CODING ACROSS MULTIPLE ZONES AND SUB-ZONES  
In various embodiments, methods and systems for erasure coding data across multiple storage zones are provided. This may be accomplished by dividing a data chunk into a plurality of sub-fragments....
US20070300130 Method of Error Correction Coding for Multiple-Sector Pages in Flash Memory Devices  
A flash memory system, including a flash memory device and a controller, and having improved efficiency error correction coding (ECC), is disclosed. Each page in the flash memory device has the...
US20140380125 ERASURE CODING ACROSS MULTIPLE ZONES  
In various embodiments, methods and systems for erasure coding data across multiple storage zones are provided. This may be accomplished by dividing a data chunk into a plurality of sub-fragments....
US20140281814 CORRECTION OF BLOCK ERRORS FOR A SYSTEM HAVING NON-VOLATILE MEMORY  
Systems and methods are disclosed for correction of block errors for a system having non-volatile memory (“NVM”). In particular, the system can store a parity page per page-modulo, where a...
US20070226592 Variable sector-count ECC  
Improved memory devices, circuitry, and data methods are described that facilitate the detection and correction of data in memory systems or devices by increasing the data area of user data being...
US20150227423 Mitigating The Impact Of A Single Point Of Failure In An Object Store  
Example apparatus and methods distribute ranges or erasure codes associated with ranges to reduce or minimize the impact of a single point of failure in an object store. Erasure codes associated...
US20150220392 STORAGE SYSTEMS WITH ADAPTIVE ERASURE CODE GENERATION  
Apparatuses, methods and storage medium associated with generating erasure codes for data to be stored in a storage system. In embodiments, a method may include launching, by storage system, a...
US20080256419 Configurable Split Storage of Error Detecting and Correcting Codes  
Memory space of a digital device may be configured for both instructions/data (op-code) and ECC or parity when required, otherwise the entire memory space may be configured for just the program...
US20070220402 Auxiliary storage device and read/write method  
Embodiments in accordance with the present invention provide an auxiliary storage device that prevents performance degradation and collects data useful for buffer failure analysis. In one...
US20080178061 SEGREGATION OF REDUNDANT CONTROL BITS IN AN ECC PERMUTED, SYSTEMATIC MODULATION CODE  
Segregation of redundant control bits in an ECC permuted, systematic modulation code. Appropriately encoding of user information via combined modulation and RS (Reed-Solomon) encoding ensures...
US20150261609 DISPERSED STORAGE NETWORK SLICE NAME VERIFICATION  
A method begins by a processing module dispersed storage error encoding data to produce a plurality of sets of encoded data slices in accordance with dispersed storage error coding parameters. The...
US20070067700 ERROR CORRECTION APPARATUS AND METHOD THEREOF  
An error correction device includes: a decoding unit, coupled to a main memory, for reading data from the main memory and performing an error detection on the data to generate a plurality of error...
US20100057994 DEVICE AND METHOD FOR CONTROLLING CACHES  
Device and method for controlling caches, comprising a decoder configured to decode additional information of datasets retrievable from a memory, wherein the decoded additional information is...
US20070038920 Information recording-reproducing apparatus and method of recording and reproducing information  
An information recording-reproducing apparatus includes a recording-reproducing unit configured to record information given by encoding the data in predetermined data blocks with an error...
US20070220401 Systems, methods, and apparatuses for using the same memory type to support an error check mode and a non-error check mode  
Embodiments of the invention are generally directed to systems, methods, and apparatuses for using the same memory type in an error check mode and a non-error check mode. In some embodiments, a...
US20140143635 TECHNIQUES FOR STORING ECC CHECKBITS IN A LEVEL TWO CACHE  
A partition unit that includes a cache for storing both data and error-correcting code (ECC) checkbits associated with the data is disclosed. When a read command corresponding to particular data...
US20140281815 Dispersed storage network file system directory  
A dispersed storage device manages a file system directory of a dispersed storage network by receiving a data object to be stored and a user file name of the data object, calculating a data...
US20140122971 LEH Memory Module Architecture Design in the Multi-Level LDPC Coded Iterative System  
A memory in a LDPC decoding system includes data banks organized into a ping-pong memory. The ping-pong memory is connected to an interleaver and a de-interleaver. The interleaver interleaves L...
US20060230330 Device and method for recording information  
A device records information in blocks having logical addresses at a physical address in a track on a record carrier. The logical addresses are translated into the physical addresses in dependence...
US20140089759 Error Correction Circuit for Data Communication Providing Parallelizable Linear Programming Decoding  
An error detection/correction system provides an electronic circuit detecting and correcting transmission errors using linear programming. Linear programming techniques are made practical for...
US20140040702 MANAGING A STORAGE ARRAY  
The present invention provides a method and apparatus of managing a storage array. The method comprises: striping the storage array to form a plurality of stripes; selecting F storage chunks from...
US20150006996 STORING DIRECTORY METADATA IN A DISPERSED STORAGE NETWORK  
A method begins by a processing module dispersed storage error encoding data to produce encoded data slices and updating directory metadata regarding storing the data in a dispersed storage...
US20080109704 Data allocation in memory chips  
In one embodiment, a memory device comprises a first partition to divide the memory device into a first segment to hold a first data block and a second segment to hold a second data block, and a...
US20150193321 GROUP WRITE TECHNIQUE FOR A BUS INTERFACE SYSTEM  
Embodiments of bus interface systems and methods of operating the same are disclosed. In one embodiment, a bus interface system includes a master bus controller and multiple slave bus controllers...
US20060053361 Memory devices with error detection using read/write comparisons  
A memory device includes a main memory cell array and a redundant memory cell array configured to store a first parity code for data stored in the main memory cell array. The device further...
US20110004807 LOADING SECURE CODE INTO A MEMORY  
A method of verifying the integrity of code in a programmable memory, the method including: receiving the code from an insecure memory; generating error detection bits for the code as it is...
US20140331106 CALCULATION OF ANALOG MEMORY CELL READOUT PARAMETERS USING CODE WORDS STORED OVER MULTIPLE MEMORY DIES  
A method includes, in a memory that includes two or more memory units, storing a code word of an Error Correction Code (ECC) that is representable by a plurality of check equations, such that a...
US20150067445 ADJUSTING A DISPERSAL PARAMETER OF DISPERSEDLY STORED DATA  
A method begins by a processing module storing data files utilizing a dispersed storage error coding function that includes a pillar width parameter and a decode threshold parameter. The method...
US20070255999 Memory Arrangement And Method For Error Correction  
A method of error correction for a memory arrangement includes dividing information to be written to the memory arrangement into n data blocks of m bits each, writing the n data blocks to at least...
US20150212886 ERROR FEEDBACK AND LOGGING WITH MEMORY ON-CHIP ERROR CHECKING AND CORRECTING (ECC)  
Error checking and correcting (ECC) may be performed in an on-chip memory where an error is corrected by a controller and not the on-chip memory. The controller may be flagged to show that an...
US20150212885 ERROR FEEDBACK AND LOGGING WITH MEMORY ON-CHIP ERROR CHECKING AND CORRECTING (ECC)  
Error checking and correcting (ECC) may be performed in an on-chip memory where an error is corrected by a controller and not the on-chip memory. The controller may be flagged to show that an...
US20090249169 SYSTEMS, METHODS, AND APPARATUSES TO SAVE MEMORY SELF-REFRESH POWER  
Embodiments of the invention are generally directed to systems, methods, and apparatuses to save dynamic random access memory (DRAM) self-refresh power. In some embodiments, the refresh frequency...
US20130311853 NON-VOLATILE MEMORY WITH EXTENDED ERROR CORRECTION PROTECTION  
Embodiments of the present disclosure provide methods and apparatuses related to NVM devices with extended error correction protection. In some embodiments, a parity cache is used to store parity...
US20130080856 NON-VOLATILE MEMORY WITH EXTENDED ERROR CORRECTION PROTECTION  
Embodiments of the present disclosure provide methods and apparatuses related to NVM devices with extended error correction protection. In some embodiments, a parity cache is used to store parity...
US20140365846 Apparatuses and Methods for Encoding Using Error Protection Codes  
Subject matter disclosed herein relates to error protection of data stored in and/or read from a memory device.
US20130262959 TEMPORARILY STORING AN ENCODED DATA SLICE  
A processing module encodes data using a dispersed storage error coding function to produce a set of encoded data slices and identifies storage units for storage of the set of encoded data slices....
US20140229797 ERROR CORRECTING CODE SCHEME UTILIZING RESERVED SPACE  
Methods, techniques, systems and apparatuses for utilizing reserved space for error correcting functionality. A cache line (“reserved line”) in a plurality of cache lines to store error correcting...
US20140089760 STORAGE OF CODEWORD PORTIONS  
Embodiments of the present disclosure describe device, methods, computer-readable media and system configurations for dividing error correcting code (“ECC”) codewords into portions and storing the...
US20150178149 METHOD TO DISTRIBUTE USER DATA AND ERROR CORRECTION DATA OVER DIFFERENT PAGE TYPES BY LEVERAGING ERROR RATE VARIATIONS  
An apparatus includes a memory and a controller. The memory includes a plurality of memory devices. Each memory device has a plurality of page types. The plurality of page types are classified...

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