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US20090292964 |
Method and System for Testing an Electronic Circuit to Identify Multiple Defects
A method for testing an electronic circuit comprises selecting a plurality of test patterns arranged in an order. The method tests an electronic circuit by applying to the electronic circuit a...
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US20090282307 |
Optimizing test code generation for verification environment
A method of optimizing test code generation is disclosed. The method generally includes the steps of (A) reading from a database (i) a plurality of assertions, (ii) a testbench and (iii) a target...
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US20090271677 |
Data Transformation Method and Related Device for a Testing System
A data transformation method for a testing system includes receiving a test signal comprising a test data and a timing information corresponding to the test data, and transforming the test data...
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US20090265597 |
SIGNAL OUTPUT DEVICE, SIGNAL DETECTION DEVICE, TESTER, ELECTRON DEVICE, AND PROGRAM
There is provided a signal output apparatus for outputting a pattern signal. The signal output apparatus includes a pattern generating section that generates waveform data of the pattern signal to...
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US20090210761 |
AC Scan Diagnostic Method and Apparatus Utilizing Functional Architecture Verification Patterns
A method, apparatus and computer program product are provided for implementing AC scan diagnostic of delay and AC scan chain defects in an integrated circuit chip under test using Functional...
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US20090183045 |
TESTING SYSTEM FOR A DEVICE UNDER TEST
A testing system for a device under test (DUT) includes a test parameter-generating device and a platform module. The test parameter-generating device stores test information, and is operable so as...
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US20090125772 |
WIRELESS EMBEDDED TEST SIGNAL GENERATION
An RF/Microwave on-chip signal source for testing an integrated circuit embedded in a substrate is provided. The signal source includes an on-chip antenna embedded in the substrate to receive a...
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US20090049354 |
Single-pass, concurrent-validation methods for generating test patterns for sequential circuits
A single-pass, concurrent validation method for generating test pattern sequences for sequential circuits maps fault objects arriving at circuit next-state lines into good next-state fault objects,...
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US20090024893 |
INTEGRATED CIRCUIT ARRANGEMENT AND DESIGN METHOD
An integrated circuit (IC) arrangement ( 10 ) comprises an integrated circuit ( 100 ) having a digital circuit portion ( 120 ) with a plurality of digital outputs ( 122 ), each of the outputs being...
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US20090024892 |
System and Method of Testing using Test Pattern Re-Execution in Varying Timing Scenarios for Processor Design Verification and Validation
A system and method processor testing using test pattern re-execution is presented. A processor re-executes test patterns using different timing scenarios in order to reduce test pattern build time...
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US20090024891 |
System and Method for Pseudo-Random Test Pattern Memory Allocation for Processor Design Verification and Validation
A system and method for pseudo-randomly allocating page table memory for test pattern instructions to produce complex test scenarios during processor execution is presented. The invention described...
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US20090013230 |
CIRCUIT ARRANGEMENT AND METHOD OF TESTING AND/OR DIAGNOSING THE SAME
To further develop a circuit arrangement ( 100; 100 ′), and in particular an application circuit, that is arranged to generate at least one test pattern, and a method of testing and/or diagnosing...
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US20090006917 |
TEST CIRCUIT FOR SUPPORTING CONCURRENT TEST MODE IN A SEMICONDUCTOR MEMORY
A test circuit is capable of simultaneously performing various test modes. The test circuit includes a concurrent test mode controller for providing a plurality of decoding signals by receiving...
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US20080313516 |
Signal Generator and User Interface for Setting Test Sequences and Parameters of a Test Signal
A signal generator generates a WiMedia ultra wideband test signal with a user interface for setting test sequences and parameters of the test signal. Parameters are set for Presentation Protocol...
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US20080270865 |
Vendor Independent Method to Merge Coverage Results for Different Designs
A method, computer program product, and data processing system for combining results regarding test sequences' coverage of events in testing a plurality of related semiconductor designs are...
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US20080263423 |
System and Method for Nonlinear Statistical Encoding in Test Data Compression
A method for test data compression includes generating a plurality of test cubes, each test cube comprising test cube data. Each test cube is compared with at least one other test cube, as test...
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US20080222473 |
TEST PATTERN GENERATING DEVICE AND TEST PATTERN GENERATING METHOD
An apparatus for LSI test has a risk place extraction unit supplied with a design information of the LSI to specify a place by estimating an error in LSI operation based on the design information...
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US20080222472 |
METHOD FOR AUTOMATIC TEST PATTERN GENERATION FOR ONE TEST CONSTRAINT AT A TIME
A method for automatically generating test patterns for an IC device includes initially generating a subset of available test patterns according to each of a plurality of test constraints for the...
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US20080201624 |
Sequential semiconductor device tester
A sequential semiconductor device tester, and in particular to a sequential semiconductor device tester is disclosed. In accordance with the sequential semiconductor device tester, a function of...
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US20080195908 |
METHOD AND APPARATUS FOR GENERATING EXPECT DATA FROM A CAPTURED BIT PATTERN, AND MEMORY DEVICE USING SAME
Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of these applied data signals have been properly captured. A first group of the...
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US20080195906 |
TEST PATTERN GENERATION APPARATUS AND TEST PATTERN GENERATION METHOD
A test pattern generation apparatus extracts processing that coincides with input combinational test confirmation processing from program test patterns stored in a file, extracts execution...
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US20080189585 |
SEMICONDUCTOR TESTING SYSTEM
There is provided a semiconductor testing system capable of achieving a higher speed in transmission of signals while holding back an increase in the number of transmission paths, and preventing...
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US20080141089 |
Semiconductor Integrated Circuit and System Lsi
In a semiconductor integrated circuit 11, there is constructed a test expected value programming circuit 100 having an input/input-output pad 103 for retrieving a ground/power-source signal ...
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US20080115027 |
Memory Model for Functional Verification of Multi-Processor Systems
Techniques are provided for modeling memory operations when generating test cases to verify multi-processor designs. Each memory operation has associated therewith a set of transfer attributes that...
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US20080104471 |
Method and apparatus for testing an IC device based on relative timing of test signals
An apparatus for testing an IC device includes a test signal generator for generating a predefined sequence of test signals that are input to the IC device. A timing skew monitor is provided for...
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US20080104470 |
Methods and apparatus for diagnosing a degree of interference between a plurality of faults in a system under test
A method for diagnosing a degree of interference between a plurality of faults in a system under test, the faults being detected by means of applying a test suite to the system under test,...
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US20080098271 |
System and Method for Verification and Generation of Timing Exceptions
The invention relates to a method for verifying one or more exceptions in a logic circuit comprising the steps of: a first step of providing an initial representation of a logic circuit; a second...
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US20080098270 |
Method For Determining Time to Failure of Submicron Metal Interconnects
The present disclosure is related to a method for determining time to failure characteristics of a microelectronics device. A test structure, being a parallel connection of a plurality of such...
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US20080092005 |
Scan Testing Interface
A system, method, and computer program product for scan testing a device under test (DUT). In one embodiment, compressed test data comprising packets are received at a serial test data input. The...
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US20080092004 |
Method and system for automated path delay test vector generation from functional tests
Disclosed herein are methods and systems for generating test vectors for use in verification of a circuit design and for hardware testing on a fabricated circuit representative of the circuit...
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US20080082887 |
System and Method for Modifying a Test Pattern to Control Power Supply Noise
A system and method for modifying a test pattern to control power supply noise are provided. A portion of a sequence of states in a test sequence of a test pattern waveform is modified so as to...
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US20080082886 |
Sub-instruction repeats for algorithmic pattern generators
An integrated circuit tester is described that utilizes methods of programming parallel coupled Algorithmic Pattern Generators (APGs) to generate test vector sequences and part commands with...
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US20080072112 |
Sequential Scan Technique Providing Reliable Testing of an Integrated Circuit
Determining a scan vector which would test an integrated circuit (IC) while ensuring counts in respective portions of the IC would not exceed corresponding thresholds. In an embodiment, the...
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US20080052586 |
Low power decompression of test cubes
Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be used...
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US20080052585 |
Integrated testing apparatus, systems, and methods
Embodiments herein may enable an algorithmic pattern generator (APG) to present iterative values of one or more operational parameters to a device under test (DUT). At each iteration, one or more...
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US20080052584 |
Test apparatus and test method
There is provided a test apparatus for testing a semiconductor device. The test apparatus includes a pattern generating section that sequentially reads and outputs waveform information to be used...
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US20080052578 |
Decompressors for low power decompression of test patterns
Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be used...
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US20080040639 |
Apparatus and Method For Generating Test Pattern Data For Testing Semiconductor Device
An apparatus and a method for generating a test pattern data for testing a semiconductor device are disclosed. In accordance with and in particular to the apparatus and the method, a test pattern...
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US20080034266 |
Tester For Testing Semiconductor Device
A tester for testing a semiconductor device is disclosed. The tester for testing the semiconductor device employs a data selector for converting a logical test pattern data transmitted from a...
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US20080034265 |
Tester For Testing Semiconductor Device
A tester for testing a semiconductor device is disclosed. In accordance with the tester, a data is fetched using a data strobe signal transmitted from a DUT, thereby increasing an accuracy of the...
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US20080028269 |
METHOD AND APPARATUS FOR CHARACTERIZING COMPONENTS OF A DEVICE UNDER TEST USING ON-CHIP TRACE LOGIC ANALYZER
A test system is disclosed wherein a device under test (DUT) includes a trace logic analyzer (TLA) that receives and stores test data. The test system includes both a master tester and a slave...
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US20080010576 |
Method for at speed testing of devices
A semiconductor device that includes a module under test that is integrated with the semiconductor device, that receives an input signal from a test module, and that provides an output signal to at...
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