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US20090172489 |
CIRCUIT ARRANGEMENT AND METHOD FOR CHECKING THE FUNCTION OF A LOGIC CIRCUIT IN A CIRCUIT ARRANGEMENT
A circuit arrangement comprising a logic circuit to be tested and a test circuit is provided. The logic circuit is designed to provide output data from input data, said output data being generated...
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US20090094497 |
DATA INVERSION REGISTER TECHNIQUE FOR INTEGRATED CIRCUIT MEMORY TESTING
A data inversion register technique for integrated circuit memory testing in which data input signals are selectively inverted in a predetermined pattern to maximize the probability of identifying...
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US20090077440 |
Apparatus and method for verifying target cicuit
A circuit verifying method is provided for a logic circuit of a first sequential circuit which outputs a first data based on an input data in synchronization with a first clock signal, and a second...
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US20080229166 |
Accelerating Test, Debug and Failure Analysis of a Multiprocessor Device
A mechanism for accelerating test, debug and failure analysis of a multiprocessor device is provided. With the mechanism, on-chip trace logic is utilized to receive internal signals from logic...
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US20080209294 |
BUILT-IN SELF TESTING OF A FLASH MEMORY
The present invention relates to a built-in self test of a flash memory device in a data processing device, particularly a mobile terminal, comprising a flash-memory having a plurality of data...
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US20080178055 |
Test pattern generation circuit having plural pseudo random number generation circuits supplied with clock signals at different timing respectively
A test pattern generation circuit has multiple pseudo random number generation circuits and a clock control circuit. The pseudo random number generation circuits are provided corresponding to the...
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US20080172551 |
OPERATION VERIFICATION METHOD FOR VERIFYING OPERATIONS OF A PROCESSOR
To verify an addition-function of a floating-point adder-subtractor in a processor, parameters such as the number of verification patterns of a verification program are set, a floating-point...
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US20080082885 |
Test circuit for testing command signal at package level in semiconductor device
A test circuit for testing a command signal at a package level in a semiconductor device includes: a logic level determining unit for determining logic levels of a plurality of command flag signals...
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US20080028268 |
Image display device and testing method of the same
It is the primary object of the present invention to provide a simple and accurate testing circuit and a testing method while occupying as small space as possible in an image display device. The...
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US20080016422 |
TEST APPARATUS, SHIFT AMOUNT MEASURING APPARATUS, SHIFT AMOUNT MEASURING METHOD AND DIAGNOSTIC METHOD
A shift amount measuring apparatus for measuring a phase shift amount of a signal under measurement which is input thereto includes a PLL circuit that generates a strobe signal which is...
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