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US20090300448 SCAN FLIP-FLOP DEVICE  
A scan flip-flop device has a scan flip-flop, a Nch insulated gate field effect transistor and a Pch insulated gate field effect transistor. The Nch insulated gate field effect transistor is...
US20090300445 METHOD AND SYSTEM FOR ALTERNATING BETWEEN PROGRAMS FOR EXECUTION BY CELLS OF AN INTEGRATED CIRCUIT  
A method and device for data processing in an integrated circuit having cells, the cells adapted for executing programs. A first program is run. In response to a waiting condition during which no...
US20090300446 Selective Per-Cycle Masking Of Scan Chains For System Level Test  
Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. The presence...
US20090292963 Method and System for Testing an Electronic Circuit  
A method for testing an electronic circuit comprises selecting a first log interval, a first log start pattern, a first log end pattern, and a first subset range of LBIST patterns from a plurality...
US20090282285 Semiconductor Integrated Circuit, Design Support Software System, And Automatic Test Pattern Generation System  
A semiconductor integrated circuit has a memory circuit having memory cells, a first register, a second register, a register selection circuit having an input to which an output of the first...
US20090271676 Detecting architectural vulnerability of processor resources  
In one embodiment, a quantum detector is provided to detect a vulnerability measure for a processor based on a processor metrics each associated with operation of a processor structure during a...
US20090254788 Techniques for Logic Built-In Self-Test Diagnostics of Integrated Circuit Devices  
A method, system and computer program product for performing real-time LBIST diagnostics of IC devices. During LBIST, stump data and identifiers of test cycles are saved in the IC device-under-test...
US20090249146 AUTOMATICALLY EXTENSIBLE ADDRESSING FOR SHARED ARRAY BUILT-IN SELF-TEST (ABIST) CIRCUITRY  
A method for testing integrated circuits (ICs) by automatically extending addressing for shared array built-in self-test (BIST) circuitry, includes polling a plurality of memories to determine...
US20090228751 METHOD FOR PERFORMING LOGIC BUILT-IN-SELF-TEST CYCLES ON A SEMICONDUCTOR CHIP AND A CORRESPONDING SEMICONDUCTOR CHIP WITH A TEST ENGINE  
A method, structure and design system for performing logic built-in-self-test (LBIST) cycles on a semiconductor chip with a plurality of logic circuits and a plurality of storage elements connected...
US20090217115 Method for Optimizing Scan Chains in an Integrated Circuit that has Multiple Levels of Hierarchy  
A method for optimizing scan chains in an integrated circuit that has multiple levels of hierarchy addresses unlimited chains and stumps and separately all other chains and stumps. Unlimited chains...
US20090210761 AC Scan Diagnostic Method and Apparatus Utilizing Functional Architecture Verification Patterns  
A method, apparatus and computer program product are provided for implementing AC scan diagnostic of delay and AC scan chain defects in an integrated circuit chip under test using Functional...
US20090204861 System and Method for Increasing the Extent of Built-In Self-Testing of Memory and Circuitry  
An integrated circuit (IC), a method of testing an IC and a method of reading test results from an IC containing built-in self-test (BIST) circuitry. In one embodiment, the IC includes: (1) an...
US20090183044 Method and circuit for implementing enhanced LBIST testing of paths including arrays  
A method and circuit implement testing of a circuit path including a memory array and logic including Logic Built in Self Test (LBIST) diagnostics, and a design structure on which the subject...
US20090172487 Multiple pBIST Controllers  
A system on a single integrated circuit chip (SoC) includes a plurality of operational circuits to be tested. A plurality of programmable built-in self-test (pBIST) controllers is connected to...
US20090144595 BUILT-IN SELF-TESTING (BIST) OF FIELD PROGRAMMABLE OBJECT ARRAYS  
A field programmable object array integrated circuit has built-in self-testing capability. The integrated circuit comprises an array of programmable objects, a plurality of interfaces, and a...
US20090138772 MICROPROCESSOR AND METHOD FOR DETECTING FAULTS THEREIN  
A method for detecting microprocessor hardware faults includes sending at least one input signal to a logic block within the microprocessor, collecting an output response to the input signal from...
US20090132883 TEST CIRCUIT  
A test circuit includes a plurality of circuit blocks having a same circuit construction and a same function, a plurality of internal test circuits each corresponding to a different one of the...
US20090113264 BUILT IN SELF TEST FOR INPUT/OUTPUT CHARACTERIZATION  
A test system in an integrated circuit includes at least one boundary scan cell. The boundary scan cell includes a first storage element and a second storage element connected in series with the...
US20090100305 REPROGRAMMABLE BUILT-IN-SELF-TEST INTEGRATED CIRCUIT AND TEST METHOD FOR THE SAME  
The present invention discloses a reprogrammable built-in-self-test integrated circuit and a test method for the same, wherein test programs are directly stored in the application program memory of...
US20090094496 System and Method for Improved LBIST Power and Run Time  
A method for improved Logic Built-In Self-Test (LBIST) includes providing a plurality of control signal sets, by an LBIST controller, to an LBIST domain comprising a plurality of LBIST satellite...
US20090089636 Method and Apparatus for Logic Built In Self Test (LBIST) Fault Detection in Multi-Core Processors  
A method, system, and computer program product for identifying failures in multi-core processors, utilizing logic built-in self test (LBIST) technology. Multi-core processors, having LBIST and...
US20090083598 METHOD FOR MONITORING AND ADJUSTING CIRCUIT PERFORMANCE  
A method for testing an integrated circuit implemented in an electronic system. The method includes placing an integrated circuit (or portion thereof) that is implemented in an operational system...
US20090063921 Staggered LBIST Clock Sequence for Noise (di/dt) Amelioration  
A method, device and system for performing on-chip testing are presented. In particular, the present invention provides a method, device and system for reducing noise due to large changes in...
US20090055698 SYSTEM, APPARATUS, AND METHOD FOR MEMORY BUILT-IN SELF TESTING USING MICROCODE SEQUENCERS  
Apparatuses, systems, and methods are disclosed for performing Built-In Self Tests (BIST) on memories. One such BIST includes loading microcode instructions into a main microcode sequencer and...
US20090024889 INTEGRATED CIRCUIT HAVING BUILT-IN SELF-TEST FEATURES  
An integrated circuit and a method of built-in self test in the integrated circuit employ an offset control node and offset capabilities with the integrated circuit in order to communicate and...
US20090019331 Integrated circuit for a data transmission system and receiving device of a data transmission system  
The invention relates to an integrated circuit for a data transmission system comprising a) a plurality of functional units, b) a TAP controller, according to IEEE 1149, having a JTAG interface,...
US20090019330 INTEGRATED CIRCUIT HAVING BUILT-IN SELF-TEST FEATURES  
An integrated circuit includes a sensor for providing a sensor output signal and a diagnostic circuit coupled to the sensor for providing a self-diagnostic signal. The self-diagnostic signal...
US20090013228 BIST DDR MEMORY INTERFACE CIRCUIT AND METHOD FOR TESTING THE SAME  
An apparatus and method for self-testing a DDR memory interface are disclosed. In one aspect, a built-in-self-test (BIST) memory interface circuit comprises a signal multiplier for receiving a...
US20080301511 INTEGRATED CIRCUIT WITH CONTINUOUS TESTING OF REPETITIVE FUNCTIONAL BLOCKS  
A method of continuous testing of repetitive functional blocks provided on an integrated circuit (IC) which includes selecting one of the repetitive functional blocks at a time for testing,...
US20080276144 Method and System for Formal Verification of Partial Good Self Test Fencing Structures  
The concept of applying fencing logic to Built-In Self Test (BIST) hardware structures for the purpose of segregating defective circuitry and utilizing the remaining good circuitry is a well known...
US20080250289 Method for Performing a Logic Built-in-Self-Test in an Electronic Circuit  
The present invention relates to a method for performing a logic built-in self-test (LBIST) on an electronic circuit with a plurality of logic circuits ( 18, 20, 22, 24 ) and storage elements ( 14,...
US20080235547 SELF-TEST OUTPUT FOR HIGH-DENSITY BIST  
A method, apparatus and system of a self-test output for high density BIST are disclosed. In one embodiment, an integrated circuit includes one or more memories, a BIST controller coupled to the...
US20080215944 Built-In Self Test (BIST) Architecture having Distributed Interpretation and Generalized Command Protocol  
Built-in self-test (BIST) architecture having distributed interpretation and generalized command protocol is disclosed. In an embodiment, a system is disclosed and includes a centralized built-in...
US20080209293 PROBING SYSTEM FOR INTEGRATED CIRCUIT DEVICES  
A probing system for integrated circuit device, which transmits testing data/signal between an automatic test equipment (ATE) and an integrated circuit device, is disclosed. The probing system...
US20080209292 CIRCUIT FOR CONTROLLING VOLTAGE FLUCTUATION IN INTEGRATED CIRCUIT  
An integrated circuit and related method for controlling voltage fluctuations. The integrated circuit includes a plurality of clock buffers and a plurality of latches synchronously operated in...
US20080195901 OP-CODE BASED BUILT-IN-SELF-TEST  
A built-in-self-test (BIST) system for testing a memory that includes a scheduler module that generates a first test algorithm based on a set of operational codes. Each operational code defines a...
US20080172587 Lowering Power Consumption During Logic Built-In Self-Testing (LBIST) Via Channel Suppression  
A method, system and computer readable medium for on-chip testing is presented. In one embodiment, the method, system or computer readable medium includes identifying which LBIST channels of a...
US20080155363 BIST CIRCUIT DEVICE AND SELF TEST METHOD THEREOF  
A BIST circuit device includes a test memory, a test result storage memory having the capacity equal to or larger than the capacity of the test memory, and a control circuit which performs a test...
US20080148119 Apparatus for Built-in Speed Grading and Method for Generating Desired Frequency for the Same  
A method for Built-In Speed Grading (BISG) comprises a Circuit Under Test (CUT) with Built-In Self-Test (BIST) circuitry, an All-Digital Phase-Locked Loop (ADPLL), and a BISG, to automatically...
US20080141089 Semiconductor Integrated Circuit and System Lsi  
In a semiconductor integrated circuit 11, there is constructed a test expected value programming circuit 100 having an input/input-output pad 103 for retrieving a ground/power-source signal ...
US20080133992 METHOD, APPARATUS AND COMPUTER PROGRAM PRODUCT FOR IMPLEMENTING SCAN-CHAIN-SPECIFIC CONTROL SIGNALS AS PART OF A SCAN CHAIN  
A method, apparatus and computer program product are provided for implementing scan-chain-specific control signals as an integral part of a scan chain. A scan input vector including scan data input...
US20080133993 ON-CHIP HIGH-SPEED SERIAL DATA ANALYZERS, SYSTEMS, AND ASSOCIATED METHODS  
Some embodiments include apparatus, systems, and methods having a digital-to-analog converter (DAC) to provide at least one DAC voltage value, a comparator to compare the at least one DAC voltage...
US20080126901 MEMORY WITH IMPROVED BIST  
An integrated circuit device includes an embedded memory having a plurality of memory macros and a built-in-self-test (BIST) circuit coupled to the plurality of memory macros for simultaneous...
US20080126900 Array delete mechanisms for shipping a microprocessor with defective arrays  
Detecting and correcting errors in arrays after ABIST testing, after ABIST testing, detected errors are faults are isolated by blowing a fuse.
US20080125990 BUILT-IN SELF TEST CIRCUIT FOR ANALOG-TO-DIGITAL CONVERTER AND PHASE LOCK LOOP AND THE TESTING METHODS THEREOF  
A BIST circuit for testing both an analog-to-digital converter and a phase lock loop includes a controllable delay circuit, a NAND gate, a dividing circuit, a NOR gate and a charge/discharge...
US20080126892 Locally synchronous shared BIST architecture for testing embedded memories with asynchronous interfaces  
A system and method of sharing testing components for multiple embedded memories and the memory system incorporating the same. The memory system includes multiple test controllers, multiple...
US20080115024 System and method for testing state retention circuits  
This invention discloses a system and method for testing a plurality of state retention circuits in an integrated circuit (IC) chip, that comprises a built-in test circuit configured to invoke a...
US20080115026 Method and Apparatus for Scheduling BIST Routines  
The content and order of a predetermined sequence of hard-coded and/or quasi-programmable test patterns may be altered during a Built-In Self-Test (BIST) routine. As such, knowledge gained post...
US20080109691 Method and Apparatus for Executing a BIST Routine  
During a Built-In Self-Test (BIST) routine, execution of a sequence of tests is re-initiated after a corrective action is taken starting with the test having the highest re-ordered priority. The...
US20080104469 Apparatus and Method for Using a Single Bank of eFuses to Successively Store Testing Data from Multiple Stages of Testing  
An apparatus and method for using a single bank of electric fuses (eFuses) to successively store test data derived from multiple stages of testing are provided. To encode and store array redundancy...
Matches 1 - 50 out of 63 1 2 >