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US20090300448 SCAN FLIP-FLOP DEVICE  
A scan flip-flop device has a scan flip-flop, a Nch insulated gate field effect transistor and a Pch insulated gate field effect transistor. The Nch insulated gate field effect transistor is...
US20090271674 SCAN TEST METHOD AND APPARATUS  
The disclosure describes a novel method and apparatus for providing expected data, mask data, and control signals to scan test architectures within a device using the falling edge of a test/scan...
US20090254787 Shift-frequency scaling  
There is provided a method that includes, (a) determining a first clock frequency for shifting a first section of a scan pattern set through a path in a digital circuit such that a first power...
US20090240997 SEMICONDUCTOR INTEGRATED CIRCUIT AND DESIGN AUTOMATION SYSTEM  
A scan chain circuit causes a plurality of flip-flops to function as shift registers during execution of a scan test and can execute a scan shift that serially transfers test pattern data for the...
US20090228752 SEMICONDUCTOR INTEGRATED CIRCUIT  
A semiconductor integrated circuit, including a data input unit for receiving an input data signal to be supplied to an external data input terminal, a storage unit for storing the input data...
US20090228751 METHOD FOR PERFORMING LOGIC BUILT-IN-SELF-TEST CYCLES ON A SEMICONDUCTOR CHIP AND A CORRESPONDING SEMICONDUCTOR CHIP WITH A TEST ENGINE  
A method, structure and design system for performing logic built-in-self-test (LBIST) cycles on a semiconductor chip with a plurality of logic circuits and a plurality of storage elements connected...
US20090217115 Method for Optimizing Scan Chains in an Integrated Circuit that has Multiple Levels of Hierarchy  
A method for optimizing scan chains in an integrated circuit that has multiple levels of hierarchy addresses unlimited chains and stumps and separately all other chains and stumps. Unlimited chains...
US20090210763 Automated System and Processing for Expedient Diagnosis of Broken Shift Registers Latch Chains Using JTAG  
This invention involves the use of the JTAG functional test patterns and exercisors to solve the problem of diagnosing broken scan chains in either a serial or a lateral broadside insertion manner...
US20090183043 SEMICONDUCTOR INTEGRATED CIRCUIT  
A semiconductor integrated circuit includes a digital circuit and a first-stage register circuit provided in a stage followed by the digital circuit. The digital circuit includes a logic circuit...
US20090150732 METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR INTEGRATED CIRCUIT RECOVERY TESTING USING SIMULATION CHECKPOINTS  
A method, system, and computer program product for integrated circuit recovery testing using simulation checkpoints is provided. The method includes executing an error injection test on an...
US20090132879 MULTIPLEXING OF SCAN INPUTS AND SCAN OUTPUTS ON TEST PINS FOR TESTING OF AN INTEGRATED CIRCUIT  
Techniques for efficiently performing scan tests are described. In an aspect, a single test pin may be used for both a scan input and a scan output for a scan chain. This multiplexing may reduce...
US20090132881 DUAL MODE TEST ACCESS PORT METHOD AND APPARATUS  
Two common varieties of test interfaces exist for ICs and/or cores, the IEEE 1149.1 Test Access Port (TAP) interface and internal scan test ports. The TAP serves as a serial communication port for...
US20090132882 Scan-load-based dynamic scan configuration  
A scan-load-based (SLB) dynamic scan configuration reconfigures scan structures via scan-load operation, thereby eliminating interconnect network distributing configuration signals, and employs...
US20090125768 REDUCED SIGNALING INTERFACE METHOD AND APPARATUS  
This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the...
US20090125770 SCAN BASED COMPUTATION OF A SIGNATURE CONCURRENTLY WITH FUNCTIONAL OPERATION  
A method and circuit for capturing and observing the internal state of an integrated circuit that utilizes a scan chain capable of capturing the functional state of an integrated circuit during...
US20090125771 Scan Based Testing of an Integrated Circuit Containing Circuit Portions Operable in Different Clock Domains during Functional Mode  
An integrated circuit containing an encoder which avoids setup/hold violation in a memory element of one clock domain, when receiving data from another memory element of another clock domain during...
US20090125769 ON-CHIP CIRCUIT FOR TRANSITION DELAY FAULT TEST PATTERN GENERATION WITH LAUNCH OFF SHIFT  
A clock pulse controller includes a test clock pulse input for receiving test clock pulses. A scan enable input receives a scan enable signal having a first state and a second state. A trigger...
US20090119562 ADAPTING SCAN ARCHITECTURES FOR LOW POWER OPERATION  
Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan...
US20090119561 Microcomputer and Method of Testing The Same  
Embodiments of the present invention provide a microcomputer on which a plurality of ICs (Integrated Circuits) connected from one another by a source-synchronous interface is mounted. The...
US20090024888 SEMICONDUCTOR DEVICE  
An object of the present invention is to provide a semiconductor device capable of recognizing circuit malfunction in an actual operation and of specifying a point of the circuit malfunction, and...
US20080313514 ON-CHIP AC SELF-TEST CONTROLLER  
A system for performing AC self-test on an integrated circuit that includes a system clock for normal operation is provided. The system includes the system clock, self-test circuitry, a first and...
US20080288843 OPTIMIZED JTAG INTERFACE  
An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than...
US20080282122 SINGLE SCAN CLOCK IN A MULTI-CLOCK DOMAIN  
Herein described are at least a method and a system to perform scan testing of an integrated circuit chip. The integrated circuit chip is scan tested using only a single scan clock. The single scan...
US20080270860 Integrated Circuit for Writing and Reading Registers Distributed Across a Semiconductor Chip  
An integrated circuit on a semiconductor chip with a plurality of registers distributed across the semiconductor chip. The registers are writeable and readable. The integrated circuit comprises a...
US20080270863 METHODS OF SYNCHRONOUS DIGITAL OPERATION AND SCAN BASED TESTING OF AN INTEGRATED CIRCUIT USING NEGATIVE EDGE FLIP-FLOPS FOR MUXSCAN AND EDGE CLOCK COMPATIBLE LSSD  
A method of synchronous digital operation and scan based testing of an integrated circuit using a flip-flop. The method including: providing a flip-flop comprising: a master latch having an input...
US20080270859 Scan test circuit and scan test control method  
A scan test circuit in the present invention includes a control FF for inputting a control signal, and a scan path chain configured of scan storage elements to operate in a, shift operation mode...
US20080250288 Scan Testing Methods  
A method of testing an integrated circuit, comprises providing a test vector to a shift register arrangement by providing test vector bits in series into the shift register arrangement ( 20 ) timed...
US20080235546 SYSTEM AND METHOD FOR DETECTING A WORK STATUS OF A COMPUTER SYSTEM  
A system for detecting a work status of a computer system is provided. The system includes a super input/output (Super I/O) chipset, a complex programmable logic device (CPLD), a South Bridge...
US20080229165 Address translation system for use in a simulation environment  
Methods and systems for simulation of a testable system are provided in which a virtual testable system is used. One method includes inputting a system definition file into a translation utility,...
US20080222471 CIRCUITRY TO PREVENT PEAK POWER PROBLEMS DURING SCAN SHIFT  
In some embodiments, a chip includes first and second scan chain segments each including registers and multiplexers to provide to the registers scan input signals during scan input periods and...
US20080209291 OVER TEMPERATURE DETECTION APPARATUS AND METHOD THEREOF  
A device is provided for detecting delays of data due to over-temperature conditions, the device includes a first latch having a data input and a clock input and an output, and a first delay path...
US20080195905 METHOD AND APPARATUS FOR SHUTTING OFF DATA CAPTURE ACROSS ASYNCHRONOUS CLOCK DOMAINS DURING AT-SPEED TESTING  
A method for testing logic devices configured across asynchronous clock domains includes deactivating, during at-speed fault testing, a local clock signal for each of a first plurality of latches...
US20080163020 Variable Clocked Scan Test Improvements  
Addition of specific test logic may improve the level of test vector compression achieved from existing variable scan test logic. Methods for determining the compressed vectors' states, given the...
US20080133992 METHOD, APPARATUS AND COMPUTER PROGRAM PRODUCT FOR IMPLEMENTING SCAN-CHAIN-SPECIFIC CONTROL SIGNALS AS PART OF A SCAN CHAIN  
A method, apparatus and computer program product are provided for implementing scan-chain-specific control signals as an integral part of a scan chain. A scan input vector including scan data input...
US20080126898 SYSTEM AND METHOD FOR GENERATING ON-CHIP INDIVIDUAL CLOCK DOMAIN BASED SCAN ENABLE SIGNAL USED FOR LAUNCH OF LAST SHIFT TYPE OF AT-SPEED SCAN TESTING  
Presented herein are system(s) and method(s) for generating a individual clock domain based scan enable signal for launch of last shift type of at-speed scan testing. In one embodiment, there is...
US20080126897 SYSTEM AND METHOD FOR GENERATING SELF-SYNCHRONIZED LAUNCH OF LAST SHIFT CAPTURE PULSES USING ON-CHIP PHASE LOCKED LOOP FOR AT-SPEED SCAN TESTING  
Presented herein are system(s) and method(s) for generating self-synchronized launch of last shift capture pulses using on-chip phase locked loop for at-speed scan testing. In one embodiment, there...
US20080120525 Method and Apparatus for Detecting and Correcting Soft-Error Upsets in Latches  
An error detection circuit for a latch precharges two dynamic nodes whose discharge paths are gated by true and complement storage nodes of the latch, such that one and only one of the dynamic...
US20080115023 SET HARDENED REGISTER  
A radiation hardened latch and a method of operation. To mitigate SET effects, the latch includes an internally located pulse rejection inverter. The pulse rejection inverter receives an input...
US20080115024 System and method for testing state retention circuits  
This invention discloses a system and method for testing a plurality of state retention circuits in an integrated circuit (IC) chip, that comprises a built-in test circuit configured to invoke a...
US20080098268 USING CLOCK GATING OR SIGNAL GATING TO PARTITION A DEVICE FOR FAULT ISOLATION AND DIAGNOSTIC DATA COLLECTION  
In one aspect, an electronic device that has been partitioned into segments by using clock gating or signal gating is tested. One of the segments that is a source of a failure is identified....
US20080092000 DELAY CIRCUIT, JITTER INJECTION CIRCUIT, AND TEST APPARATUS  
There is provided a delay circuit that delays and outputs a given input signal. The delay circuit includes a first delaying section that delays the input signal, a second delaying section that...
US20080092001 METHOD AND DEVICE FOR DATA COMMUNICATION  
A programmable logic device is presented. The device comprises a plurality of logic elements and a plurality of I/O pins; a multiplexer and/or a de-multiplexer unit. The multiplexer and/or...
US20080092002 Semiconductor integrated circuit and control method thereof  
A semiconductor integrated circuit includes a target circuit configured to operate in a normal mode, to form a scan chain to serially transfer a test data through the scan chain, in a scan path...
US20080086666 ANALYZER  
The analyzer according to the present invention is an analyzer having a scan test function, and including scan paths each having flip-flops which function as a shift register when a scan test is...
US20080086667 Chip testing device and system  
A chip testing device having a plurality of testing units is provided. Each testing unit comprises a selector, a flip-flop unit, a first buffer and a second buffer. The selector is controlled by a...
US20080082882 DOUBLE-EDGE TRIGGERED SCANNABLE PULSED FLIP-FLOP FOR HIGH FREQUENCY AND/OR LOW POWER APPLICATIONS  
A circuit for data storage is presented. The circuit includes clock generation circuits for generating a pulse clock signal having first and second clock pulses for each clock cycle of a system...
US20080082880 METHOD OF TESTING HIGH-SPEED IC WITH LOW-SPEED IC TESTER  
A low-frequency circuit tester tests a high-frequency circuit to determine whether the circuit will operate properly at its specified operating frequency when clocked by a clock signal having a...
US20080082881 In situ processor margin testing  
Embodiments of apparatuses, methods, and systems for in situ processor margin testing are disclosed. In one embodiment, an apparatus includes virtual machine control logic and operating point...
US20080052580 Signal output circuit, and test apparatus  
A signal output circuit for outputting an output signal in accordance with a predetermined system timing is provided. The signal output circuit includes a shift register that delays an input signal...
US20080052579 System and Method for Advanced Logic Built-in Self Test with Selection of Scan Channels  
A system and method for advanced logic built-in self test with selection of scan channels is present. An LBIST controller loads scan patterns into a device's scan channels through sequential or...
Matches 1 - 50 out of 58 1 2 >