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US20120017128 SYSTEM FOR TREE SEQUENCE TESTING OF A DEVICE AND METHOD FOR TREE SEQUENCE TESTING OF A DEVICE IN A TEST FRAMEWORK ARCHITECTURE  
A system comprises a test framework architecture for tree sequence testing of a device, comprising a plurality of hierarchical layers at least comprising an upmost layer and a lowest layer, each...
US20110099439 AUTOMATIC DIVERSE SOFTWARE GENERATION FOR USE IN HIGH INTEGRITY SYSTEMS  
Systems, devices and methods of automatic diverse software generation are disclosed. In an embodiment, a method includes providing a base algorithm implementation related to a first hardware...
US20130061104 IMPROVEMENTS IN BACKWARD ANALYSIS FOR DETERMINING FAULT MASKING FACTORS  
A method and a system are presented for determining the observability of faults in an electronic circuit. In the method, for each element the time periods are determined in which an occurrent...
US20050172181 System and method for production testing of high speed communications receivers  
A method for testing a semiconductor device with a multi-gigabit communications receiver includes combining a data output from a high-speed communications transmitter with a perturbation signal...
US20140351664 TESTING AN INTEGRATED CIRCUIT  
Testing an integrated circuit in a test environment that includes a virtual test engine and a test system with an integrated circuit tester. The integrated circuit is connected to the virtual test...
US20140195868 OPERATION MANAGEMENT DEVICE, OPERATION MANAGEMENT METHOD  
An operation management to grasp a metric in which a continuous abnormality has occurred in a system, easily, is provided. An operation management apparatus 100 includes a metric collection unit...
US20130124933 ASICS HAVING PROGRAMMABLE BYPASS OF DESIGN FAULTS  
A relatively small amount of programmable logic may be included in a mostly ASIC device such that the programmable logic can be used as a substitute for a fault-infected ASIC block. This...
US20150100839 GENERALIZED MODULAR REDUNDANCY FAULT TOLERANCE METHOD FOR COMBINATIONAL CIRCUITS  
The generalized modular redundancy fault tolerance method for combinational circuits utilizes redundancy techniques to improve soft error reliability and is based on probability of occurrence for...
US20070288813 Cell board interconnection architecture with serviceable switch board  
In certain embodiments, there is provided a computer system and a method for providing a computer system. Specifically, there is provided a computer system that may include a porous main board...
US20130166974 METHODS AND SYSTEMS FOR LOGIC DEVICE DEFECT TOLERANT REDUNDANCY  
Provided is an apparatus including a scheduler and a plurality of logic devices coupled to the scheduler, each including a defect indicator. The scheduler determines whether one or more of the...
US20120166898 SINGLE LEVEL OF METAL TEST STRUCTURE FOR DIFFERENTIAL TIMING AND VARIABILITY MEASUREMENTS OF INTEGRATED CIRCUITS  
A test structure for an integrated circuit device includes one or more experiments selectively configured to receive one or more high-speed input signals as inputs thereto and to output at least...
US20110078525 Method and Apparatus of ATE IC Scan Test Using FPGA-Based System  
An apparatus and a method for enhancing the use of automated test equipment (ATE), are presented. The apparatus comprises a test load board that mounts a plurality of devices to be tested (DUTs),...
US20080133988 FPGA Programming Structure for ATPG Test Coverage  
Testing of combinatorial logic in a programmable device is provided by routing input and/or output test values as signals from and back to dedicated logic through programming circuitry in...
US20120159272 METHODS OF INCREASING FIDELITY OF QUANTUM OPERATIONS  
Systems and methods are provided for improving fidelity of a quantum operation on a quantum bit of interest. A controlled quantum gate operation, controlled by the quantum bit of interest, id...
US20080163015 Framework for automated testing of enterprise computer systems  
An automated testing framework enables automated testing of complex software systems. The framework can be configured for test selection, flow definition, and automated scheduled testing of...
US20070079189 Method and system for generating a global test plan and identifying test requirements in a storage system environment  
The present invention is directed to a system and method for a quality assurance tool generating test plans and identifying new test requirements for a new version of a product. Old versions of...
US20070220381 Enhanced diagnosis with limited failure cycles  
Chain or logic diagnosis resolution can be enhanced in the presence of limited failure cycles using embodiments of the various methods, systems, and apparatus described herein. For example,...
US20110022906 METHOD AND SYSTEM FOR TEST POINT INSERTION  
It is desired to suppress an increase of the TAT or a repetition of processing in inserting a test circuit on designing. A test point insertion method includes: extracting a plurality of logic...
US20070094557 Semiconductor integrated circuit tester  
A semiconductor integrated circuit tester includes a host computer having a parallel data bus segment, a test head including at least one instrument having a parallel data bus segment, a first...
US20090172282 DIGITAL CIRCUITS AND METHODS FOR TESTING A DIGITAL CIRCUIT  
Digital circuits and methods for testing a digital circuit are disclosed. One embodiment provides a digital circuit having a first plurality of storage elements, and a second plurality of storage...
US20050039091 Monitoring printer via network  
Amounts of expendables consumed by a printer are sensed accurately. A job control unit 106 transfers a print job queued in job buffer 107 to a spooler 105, in page units. Spooler 105 sends the...
US20110271156 APPARATUS AND METHOD FOR TESTING SHADOW LOGIC  
A system for testing faults in shadow logic includes a sequential block coupled to a shadow logic block and a delaying block to receive test patterns for testing the shadow logic block. The...
US20080141084 SYSTEM FOR ESTIMATING AND IMPROVING TEST CASE GENERATION  
A technique for estimating and improving the test coverage for large machines, while accumulating minimum information of past test cases (i.e., minimum feedback) is provided. The technique is...
US20120131401 SYSTEM AND METHOD FOR SHARING A COMMUNICATIONS LINK BETWEEN MULTIPLE COMMUNICATIONS PROTOCOLS  
A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to exchange information with other systems...
US20090024893 INTEGRATED CIRCUIT ARRANGEMENT AND DESIGN METHOD  
An integrated circuit (IC) arrangement (10) comprises an integrated circuit (100) having a digital circuit portion (120) with a plurality of digital outputs (122), each of the outputs being...
US20070208973 PCI-E debug card  
A PCI-E debug card includes an insertion part, a low-pin-count pin set, a power pin, a ground pin, a decoder and a display unit. The insertion part is for connecting to a PCI-E slot. The...
US20050204217 Identical core testing using dedicated compare and mask circuitry  
Today large system-on-chips (SOC) are designed using predefined circuit functions commonly referred to as cores. In some cases, multiple instances of the same core may be implemented within an SOC...
US20110320895 Test circuit for testing execution of a handshake protocol and method for testing execution of handshake protocol  
The present invention relates to a checker circuit for a handshake protocol. The checker circuit detects common errors that occur when two communication unit on execute the handshake protocol. The...
US20070226560 Electronic circuit and integrated circuit including scan testing circuit, and power consumption reducing method used for integrated circuit  
An integrated circuit with a scan testing circuit which enables reducing power consumption in normal operation mode is provided. A power-supply controller applies a power-supply voltage to...
US20070226559 MULTIMEDIA DEVICE TESTING METHOD  
A multimedia device testing method is provided. The multimedia device testing method includes providing test files of each test signal according to parameters of each test signal via a computer;...
US20080082876 Power gating in integrated circuits for leakage reduction  
A system is disclosed for reducing current leakages in an integrated circuit (IC), the system comprises one or more separated power supply lines connecting between one or more power sources and an...
US20060156115 Device, system, and method for providing error information in XHT network  
A device, a system, and a method for displaying error information within an expandable Home Theater (XHT) network, and more particularly, to a device, a system, and a method for providing error...
US20070011519 Semiconductor failure analysis apparatus, failure analysis method, failure analysis program, and failure analysis system  
A failure analysis apparatus 10 is composed of an inspection information acquirer 11 for acquiring at least a pattern image P1 of a semiconductor device, a layout information acquirer 12 for...
US20080034260 Method for structured storage of error entries  
In a method for structured storage of error entries of the users of a data bus in a motor vehicle, upon occurrence of an error, a function possibly influenced by the error and the members of an...
US20070113124 Method of testing integrated circuit and apparatus therefor  
In a method of testing integrated circuit (IC), a personal computer host and related software and hardware are used to constitute a system for conducting and controlling IC test. The method...
US20070113126 Testing and Recovery in a Multilayer Device  
Disclosed are systems and methods of producing electronic devices including an auxiliary circuit mounted on another, underlying, circuit at the wafer level. The auxiliary circuit is electrically...
US20050229055 Interface circuit for a single logic input pin of an electronic system  
An interface circuit for a single logic input pin of an electronic system, comprising a decoder for converting a pulse coded signal applied to said pin to a sequence of logic low and logic high...
US20080082877 Integrated testing system for wireless and high frequency products and a testing method thereof  
A testing system selects one of testing paths based on a control unit and a test switching unit for randomly executing tests upon a plurality of products based on the testing requirements of each...
US20120054567 MULTIMEDIA DEVICE TEST SYSTEM  
A test system includes a supervisor unit coupled to a control interface, the control interface coupled to first and second test modules. Each test module may include a first logic module to test...
US20090055695 INTEGRATED CIRCUIT WITH SELF-TEST FEATURE FOR VALIDATING FUNCTIONALITY OF EXTERNAL INTERFACES  
This disclosure describes an integrated circuit with self-test features for validating functionality of external interfaces. Example external interfaces include memory interfaces and bus...
US20060195735 Circuit for distributing a test signal applied to a pad of an electronic device  
The circuit distributes a test signal applied to a pad of an electronic device that is enabled during test phases of the device and disabled during normal functioning. The circuit includes a...
US20060069969 Inversion based stimulus generation for device testing  
A device testing apparatus and method for testing a semiconductor device is provided. For device testing, stimulus data is generated and provided to the semiconductor device, and output data of...
US20050138500 Functional test design for testability (DFT) and test architecture for decreased tester channel resources  
According to one aspect of the present invention, multiple pins of a chip are connected to a single test channel of a tester. This allows an older tester with fewer test channels to be used with...
US20110246843 ERROR DETECTION IN PRECHARGED LOGIC  
An integrated circuit is provided with domino logic including a speculative node and a checker node. Precharged circuitry precharges both the speculative node and the checker node. Logic circuitry...
US20120324302 INTEGRATED CIRCUIT FOR TESTING USING A HIGH-SPEED INPUT/OUTPUT INTERFACE  
An integrated circuit configured for testing is described. The integrated circuit includes a high-speed input/output interface. The integrated circuit also includes a test controller coupled to...
US20150019927 TEST SYSTEM AND DEVICE  
An aspect of the present invention is to provide a test system for detecting whether a continuity fault condition, e.g., a short or open condition, exists in the path between a tester and chips on...
US20070162798 Single event upset error detection within an integrated circuit  
An integrated circuit 2 includes logic circuitry 10 and sequential storage elements 8. Both the logic circuit 10 and sequential storage elements 8 can be subject to particle strikes giving rise to...
US20070283200 SCAN COMPRESSION ARCHITECTURE FOR A DESIGN FOR TESTABILITY COMPILER USED IN SYSTEM-ON-CHIP SOFTWARE DESIGN TOOLS  
A scan compression architecture for a design for testability compiler used in system-on-chip software design tools includes a first scan architecture including a first scan compressor/decompressor...
US20150149842 TEST DEVICE AND METHOD USING A SEPARATE CONTROL MODULE FOR TEST  
A test device and method using a separate control module for test are disclosed, where a main console is replaced with a control module of the test device, the control module may generate a...
US20070234149 Checking the integrity of programs or the sequencing of a state machine  
A method and a circuit for protecting the execution of a calculation by an electronic circuit, conditioning a result of the calculation to states of bits indicative of executions of steps of...

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