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US20090319841 STRUCTURE AND APPARATUS FOR A ROBUST EMBEDDED INTERFACE  
A design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure includes an input register coupled to a data...
US20090300442 Field mounting-type test apparatus and method for testing memory component or module in actual PC environment  
Provided are a field mounting-type test apparatus and method, which can enhance competitiveness of a product by simulating various test conditions including a mounting environment so as to improve...
US20090300445 METHOD AND SYSTEM FOR ALTERNATING BETWEEN PROGRAMS FOR EXECUTION BY CELLS OF AN INTEGRATED CIRCUIT  
A method and device for data processing in an integrated circuit having cells, the cells adapted for executing programs. A first program is run. In response to a waiting condition during which no...
US20090282302 Multi-Stage Data Processor With Signal Repeater  
A signal processing device having a plurality of processing stages, each of the plurality of processing stages being adapted for applying an input signal to each of at least one item under...
US20090265595 MULTIPLE TEST ACCESS PORT PROTOCOLS SHARING COMMON SIGNALS  
A method of causing an interface to implement a mode from a plurality of selectable modes in which the interface operates according to a plurality of states defined by a state machine comprises...
US20090259897 Logic circuit protected against transient disturbances  
The invention concerns a circuit protected against transitory perturbations, comprising a combinatorial logic circuit ( 10 ), having at least an output (A); a circuit ( 20 ) generating an error...
US20090249141 SEMICONDUCTOR INTEGRATED CIRCUIT  
A semiconductor integrated circuit includes a flipflop holding and outputting input data according to a clock, the flipflop having: an input end to which data is input; an output end from which...
US20090228749 METHOD AND APPARATUS FOR SELECTIVELY COMPACTING TEST RESPONSES  
A method and apparatus to compact test responses containing unknown values or multiple fault effects in a deterministic test environment. The proposed selective compactor employs a linear compactor...
US20090228752 SEMICONDUCTOR INTEGRATED CIRCUIT  
A semiconductor integrated circuit, including a data input unit for receiving an input data signal to be supplied to an external data input terminal, a storage unit for storing the input data...
US20090204860 Data signal handling circuitry and methods with error analysis capabilities  
To help identify a noise (interference) source in an electronic device that may be causing data errors in the device, relatively low level data receiver circuitry in the device is provided with one...
US20090172484 Method for Implementing a Serialization Construct Within an Environment of Parallel Data Flow Graphs  
A serialization construct is implemented within an environment of a number of parallel data flow graphs. A quiesce node is appended to every active data flow graph. The quiesce node prevents a...
US20090172282 DIGITAL CIRCUITS AND METHODS FOR TESTING A DIGITAL CIRCUIT  
Digital circuits and methods for testing a digital circuit are disclosed. One embodiment provides a digital circuit having a first plurality of storage elements, and a second plurality of storage...
US20090164861 METHOD AND APPARATUS FOR A CONSTRAINED RANDOM TEST BENCH  
A constrained random test bench methodology employing an instruction abstraction layer. The instruction abstraction layer includes an instruction streamer for generating random test instruction...
US20090144595 BUILT-IN SELF-TESTING (BIST) OF FIELD PROGRAMMABLE OBJECT ARRAYS  
A field programmable object array integrated circuit has built-in self-testing capability. The integrated circuit comprises an array of programmable objects, a plurality of interfaces, and a...
US20090144594 METHOD AND APPARATUS FOR DESCRIBING AND TESTING A SYSTEM-ON-CHIP  
The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of...
US20090138769 Test System Having A Sub-System To Sub-System Bridge  
A test system having a sub-system to sub-system bridge may be provided that utilizes the useful attributes of a plurality of circuit testing techniques, while reducing deficiencies associated with...
US20090125768 REDUCED SIGNALING INTERFACE METHOD AND APPARATUS  
This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the...
US20090125765 Apparatus for Certifying Hardware Abstraction Layer in Mobile Terminal and Method Thereof  
Provided is an apparatus and method for certifying a hardware abstraction layer in a mobile terminal. The apparatus includes: a communication unit for receiving a predetermined test case from an...
US20090125766 METHOD, SYSTEM AND COMPUTER PROGRAM FOR HARDWARE DESIGN DEBUGGING  
A plurality of diagnosis methods are provided for enabling hardware debugging. A first diagnosis method enables hardware debugging by means of time abstraction. A second diagnosis method enables...
US20090113261 CONVERSION DEVICE, CONVERSION METHOD, PROGRAM, AND RECORDING MEDIUM  
Provided are a conversion device and the like for converting a initial test pattern given in advance into a test pattern of a bit constitution of different logic values, without losing the fault...
US20090113260 TEST SYSTEM  
A test system for testing a plurality of devices under test is disclosed. The test system includes a tester and a plurality of processors. The tester is used for providing a plurality of control...
US20090077438 CIRCUIT INTERCONNECT TESTING ARRANGEMENT AND APPROACH THEREFOR  
Logic level crossings in an integrated circuit are detected. According to an example embodiment, a reset signal is provided to a flip-flop ( 314 ) as a function of a logic level of an integrated...
US20090070644 METHOD AND APPARATUS FOR DYNAMICALLY DETERMINING TESTER RECIPES  
A method includes retrieving a group test parameter determined based on test results associated with a plurality of integrated circuit devices. A particular integrated circuit device is tested...
US20090055695 INTEGRATED CIRCUIT WITH SELF-TEST FEATURE FOR VALIDATING FUNCTIONALITY OF EXTERNAL INTERFACES  
This disclosure describes an integrated circuit with self-test features for validating functionality of external interfaces. Example external interfaces include memory interfaces and bus...
US20090049352 CONTROL APPARATUS AND METHOD FOR CONTROLLING MEASURING DEVICES TO TEST ELECTRONIC APPARATUSES  
An electronic apparatus testing method is provided. The method includes the step of: reading a product ID of the electronic apparatus when the electronic apparatus is connected to a control...
US20090044063 Semiconductor memory device and test system of a semiconductor memory device  
A semiconductor memory device includes a memory core unit, N data output buffers, N data output ports, and a plurality of test logic circuits. The memory core unit stores test data through N data...
US20090024893 INTEGRATED CIRCUIT ARRANGEMENT AND DESIGN METHOD  
An integrated circuit (IC) arrangement ( 10 ) comprises an integrated circuit ( 100 ) having a digital circuit portion ( 120 ) with a plurality of digital outputs ( 122 ), each of the outputs being...
US20090013224 INTEGRATED CIRCUIT WITH BLOCKING PIN TO COORDINATE ENTRY INTO TEST MODE  
An integrated circuit (IC) including a blocking pin. An IC may include state logic, a test control unit configured to coordinate access by external circuitry to operating state of the state logic...
US20090006917 TEST CIRCUIT FOR SUPPORTING CONCURRENT TEST MODE IN A SEMICONDUCTOR MEMORY  
A test circuit is capable of simultaneously performing various test modes. The test circuit includes a concurrent test mode controller for providing a plurality of decoding signals by receiving...
US20080301509 METHOD AND APPARATUS FOR TESTING INTEGRATED CIRCUITS BY EMPLOYING TEST VECTOR PATTERNS THAT SATISFY PASSBAND REQUIREMENTS IMPOSED BY COMMUNICATION CHANNELS  
Embodiments of an apparatus and method for high-speed testing of a device under test are described herein, where the device under test is coupled to a tester via a limited passband communication...
US20080263421 Electrical Diagnostic Circuit and Method for the Testing and/or the Diagnostic Analysis of an Integrated Circuit  
An electrical diagnostic circuit and testing method is disclosed. In one embodiment the electrical diagnostic circuit for testing an integrated circuit includes a number of external inputs, a...
US20080258758 EMBEDDED SYSTEM AND CONTROL METHOD THEREFOR  
An embedded system having a programmable logic circuit, a plurality of storage devices each storing configuration data defining circuit information of the logic circuit, a setting information...
US20080263418 System and Method for Adaptive Nonlinear Test Vector Compression  
A system comprises a decompressor configured to receive an input test vector and to generate an output vector in response to the input test vector. A decoder couples to the decompressor and...
US20080256404 FAULT LOCATION ESTIMATION SYSTEM, FAULT LOCATION ESTIMATION METHOD, AND FAULT LOCATION ESTIMATION PROGRAM FOR MULTIPLE FAULTS IN LOGIC CIRCUIT  
A fault location estimation system comprises single-fault-assumed diagnostic means that assumes a single fault and stores fault candidates, fault types, and detected error-observation nodes at...
US20080250279 Method of Increasing Path Coverage in Transition Test Generation  
A method for automatically generating test patterns for digital logic circuitry using an automatic test pattern generation tool. The method includes generating test patterns and applying faulty...
US20080250280 Sharing routing of a test signal with an alternative power supply to combinatorial logic for low power design  
A device shares an existing test signal routing trace with an alternative power supply delivery channel to portions of registers located in combinatorial logic sections.
US20080250282 SERIAL I/O USING JTAG TCK AND TMS SIGNALS  
The present disclosure describes a novel method and apparatus of using the JTAG TAP's TMS and TCK terminals as a general purpose serial Input/Output (I/O) bus. According to the present disclosure,...
US20080235542 Electronic testing device for memory devices and related methods  
Described are an electronic testing device for memory devices and related methods. The testing device, comprises a memory controller managing a transfer of data and a controller buffer disposed...
US20080235543 CONVERSION DEVICE, CONVERSION METHOD, PROGRAM, AND RECORDING MEDIUM  
Provided are a conversion device and others for converting a test vector set so as to reduce a logic value difference generated before and after scan capture in outputs of scan cells included in a...
US20080222467 METHOD OF CONTROLLING A TEST MODE OF CIRCUIT  
A test vector decode circuit includes a lockout circuit to prevent inadvertent latching of output vectors. The test vector decode circuit is driven by an additional output vector from the test...
US20080222465 Checkpointing user design states in a configurable IC  
Some embodiments provide a configurable integrated circuit (IC) that has several configurable circuits and several user design state (UDS) circuits. The UDS circuits store user-design state values....
US20080222466 Meeting point thread characterization  
An apparatus associated with identifying a critical thread based on information gathered during meeting point processing is provided. One embodiment of the apparatus may include logic to...
US20080215947 Debug Circuit and a Method of Debugging  
A debug circuit for a multi-mode circuit driven by a clock signal, with an input for a clock signal, and a debug signal generator arranged to generate for each of a subset of the modes of the...
US20080209286 LOGIC CIRCUITRY AND RECORDING MEDIUM  
Logic circuitry has a test point to detect a signal about a delay fault propagating on a logic path between an input terminal and an output terminal, the test point being coupled to the logic path,...
US20080209285 Method and Circuit for Measuring Operating and Leakage Current of Individual Blocks Within an Array of Test Circuit Blocks  
A method and circuits for measuring operating and leakage current of individual blocks within an array of test circuit blocks provides measurement free of error due to leakage currents through...
US20080169823 Apparatus and Method for High-Speed SAS Link Protocol Testing  
An apparatus for changing a connection between two serial components on the same circuit board. The apparatus comprises at least one column, and each column includes first, second, third and fourth...
US20080163015 Framework for automated testing of enterprise computer systems  
An automated testing framework enables automated testing of complex software systems. The framework can be configured for test selection, flow definition, and automated scheduled testing of complex...
US20080155364 Non-volatile memory device and method for operating the memory device  
A non-volatile memory may include a flag cell array, wherein each flag cell is arranged in the memory cell array interspersed among the plurality of memory cells. The flag cell array may include a...
US20080141083 INTEGRATED CIRCUIT WITH JTAG PORT, TAP LINKING MODULE, AND OFF-CHIP TAP INTERFACE PORT  
An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP of another IC. The Off Chip TAP...
US20080141084 SYSTEM FOR ESTIMATING AND IMPROVING TEST CASE GENERATION  
A technique for estimating and improving the test coverage for large machines, while accumulating minimum information of past test cases (i.e., minimum feedback) is provided. The technique is...
Matches 1 - 50 out of 82 1 2 >