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US20110022901 METHOD FOR TESTING HARD DISKS UNDER AN EXTENSIBLE FIRMWARE INTERFACE  
A method for testing hard disks under an extensible firmware interface (EFI) provides a device tree of hard disks. Nodes of the device tree represent block devices or file systems of the hard...
US20130124932 Solid-State Disk Manufacturing Self Test  
A Solid-State Disk (SSD) Manufacturing Self Test (MST) capability enables an SSD manufacturer to generate and load tests onto SSDs, run the tests, and gather results. The SSDs self execute the...
US20140047284 COMBO STATIC FLOP WITH FULL TEST  
A SRAM (Static Random Access Memory) macro test flop circuit includes a flip-flop circuit, a scan control circuit, and an output buffer circuit. The flip-flop circuit includes a master latch...
US20130166973 STORAGE-MEDIUM DIAGNOSIS DEVICE, STORAGE-MEDIUM DIAGNOSIS METHOD  
A storage-medium diagnosis includes a storage unit that stores therein respective diagnosis results of subregions of a storage region of a storage medium; a higher-access executing unit that...
US20060200714 Test equipment for semiconductor  
A test equipment for semiconductor according to the present invention comprises a equipment main body and a memory cell provided in an outside of the equipment main body, wherein the equipment...
US20110161754 REVISION SYNCHRONIZATION OF A DISPERSED STORAGE NETWORK  
A method begins by a processing module receiving a write request message from a dispersed storage (DS) processing module, wherein the write request message includes a slice name, a DS processing...
US20110271156 APPARATUS AND METHOD FOR TESTING SHADOW LOGIC  
A system for testing faults in shadow logic includes a sequential block coupled to a shadow logic block and a delaying block to receive test patterns for testing the shadow logic block. The...
US20120047409 SYSTEMS AND METHODS FOR GENERATING DYNAMIC SUPER BLOCKS  
Systems and methods are disclosed for generating dynamic super blocks from one or more grown bad blocks of a non-volatile memory (“NVM”). In some embodiments, a dynamic super block can be formed...
US20090217111 EVALUATION METHOD AND EVALUATION SYSTEM FOR SEMICONDUCTOR STORAGE DEVICE  
An evaluation method is proposed to evaluate reliability of a nonvolatile memory in a semiconductor storage device with respect to data writing and data reading. While power is being supplied to...
US20070061639 Semiconductor device test system with test interface means  
One aspect of the invention relates to a semiconductor device test system, interface means for use with a semiconductor device test method, and a semiconductor device test method, wherein, in a...
US20150143186 SYSTEMS AND METHODS FOR DETECTING A DIMM SEATING ERROR  
DIMM seating errors may be detected. An example detection method includes determining whether a training error has occurred for a number of dynamic random access memories (DRAMs) of a DIMM. The...
US20090249137 TESTING MODULE, TESTING APPARATUS AND TESTING METHOD  
There is provided a testing module including a designation information storing section that stores thereon designation information designating an order of decoding fundamental patterns, a...
US20140189448 DECREASING POWER SUPPLY DEMAND DURING BIST INITIALIZATIONS  
Aspects of the invention provide for decreasing the power supply demand during built-in self test (BIST) initializations. In one embodiment, a BIST architecture for reducing the power supply...
US20100037108 HIGH-SPEED SEMICONDUCTOR MEMORY TEST DEVICE  
A semiconductor test device includes; a tester providing a first clock signal, first test data, a control signal and a first clock signal, a reference clock generating unit generating a reference...
US20110320891 Driving Method of Electronic Device  
A method for driving an electronic device stably is provided. The electronic device includes a power supply circuit to which power is fed by power sequentially supplied from a contactless power...
US20080201620 METHOD AND SYSTEM FOR UNCORRECTABLE ERROR DETECTION  
A system, method and program product for utilizing error correction code (ECC) logic to detect multi-bit errors. In one embodiment, a first test pattern and a second test pattern are applied to a...
US20080115018 Control system for an optical storage device  
A control system determines read performance of an optical storage device according to lock performance of a re-timing signal. The control system includes a filtering and re-timing unit for...
US20090254784 SEMICONDUCTOR MEMORY DEVICE AND SYSTEM USING SEMICONDUCTOR MEMORY DEVICE  
A semiconductor memory device comprises a RAM (Random Access Memory), an ODT (On-Die Termination) circuits and a JTAG (Joint Test Action Group) circuit. The RAM is connected to a data input-output...
US20150052409 FLEXIBLE INTERRUPT GENERATION MECHANISM  
In a testing device, a method for implementing efficient interrupt routing. The method includes receiving an interrupt from a plurality of interrupt causes, consulting an interrupt routing table...
US20090199057 March DSS: Memory Diagnostic Test  
Diagnostic march tests are powerful tests that are capable of detecting, identifying and locating faults in memories. While March SS was published for detecting simple static faults, no test has...
US20080168317 Linked Random Access Memory (RAM) Interleaved Pattern Persistence Strategy  
A method and apparatus is provided for detecting random access memory (RAM) failure for data with a plurality of addresses. The method comprises generating a plurality of RAM test patterns in a...
US20060107133 Tampering-protected microprocessor system and operating procedure for same  
A tampering-protected microprocessor system includes a microprocessor, an internal write/read memory integrated with the microprocessor into a common module, and a second memory in which at least...
US20050060620 Method of increasing capacity of an optical disc  
A system that provides increased storage capacity on optical discs includes addressing digital sum variance issues, inter-symbol interference and enhancing detection schemes by means of variable...
US20070250283 Maintenance and Calibration Operations for Memories  
Embodiments of the present invention provide methods, systems and apparatus for performing memory maintenance and calibration operations. To perform calibration operations, calibration data may...
US20070162792 METHOD FOR INCREASING THE MANUFACTURING YIELD OF PROGRAMMABLE LOGIC DEVICES  
A method for increasing the manufacturing yield of field programmable gate arrays (FPGAS) or other programmable logic devices (PLDs). An FPGA or other PLD is formed in several sections, each of...
US20060041798 Design techniques to increase testing efficiency  
Specific test logic may be added into a semiconductor logic or memory device, which does not change the normal operation of the device, but which allows under test mode the device to perform both...
US20070061638 Multi drive test system for data storage device  
Embodiments of the invention provide a data storage device test method and data storage device manufacture method which allow a tester to perform an operation test of plural data storage devices...
US20140068358 Systems and Methods for Non-Zero Syndrome Based Processing  
The present invention is related to systems and methods for harmonizing testing and using a storage media.
US20080109689 Test system improving signal integrity by restraining wave reflection  
A test system that tests a plurality of memories comprises a tester, a test board coupled to the tester, and a transmission line. The test board includes the plurality of memories. A transmission...
US20080077830 Internal signal monitoring device in semiconductor memory device and method for monitoring the same  
An internal signal monitoring device in a semiconductor memory device includes: an internal signal input unit to receive an internal signal to be monitored and having an output to provide a...
US20090282305 STORAGE SYSTEM WITH DATA RECOVERY FUNCTION AND METHOD THEREOF  
A storage system with a data recovery function and its method reduce errors in a storage medium to a recoverable range of a general ECC function by repeating a testing and recovery procedure for...
US20090150728 HIGH SPEED SERIAL TRACE PROTOCOL FOR DEVICE DEBUG  
Tracing of test information from a hardware device for debugging is formatted for transmission via a high-speed serial protocol. Data from various components in the hardware device is transmitted...
US20130111282 FAST PARALLEL TEST OF SRAM ARRAYS  
Systems and methods for performing parallel test operations on Static Random Access Memory (SRAM) cells are disclosed. In general, each parallel test operation is a test operation performed on a...
US20090193302 SEMICONDUCRTOR DEVICE  
A semiconductor device capable of reducing a memory area of a test circuit required for storing fail-information is provided. In the test circuit, for determining right/wrong of information...
US20090006912 Semiconductor memory device having burn-in test mode and method for driving the same  
A semiconductor memory device includes: a pattern selector configured to receive a first test control signal and a second test control signal to output a plurality of pattern selection signals and...
US20080126891 MEMORY LIFETIME GAUGING SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT  
An apparatus, method, and computer program product are provided for identifying at least one aspect associated with a lifetime of memory. Further, an indicia is visually displayed reflecting the...
US20080288835 Test method, integrated circuit and test system  
The test method, integrated circuit and test system embodiments disclosed herein relate to testing at least one integrated circuit which uses an internal operating clock and has a first number of...
US20090083592 SEMICONDCUTOR DEVICE, MEMORY SYSTEM AND CONTROL METHOD OF THE SEMICONDUCTOR DEVICE  
A semiconductor device including a logic circuit and a test circuit is provided which comprises: a logic signal terminal that supplies a signal to the logic circuit; a latch circuit that latches a...
US20100083062 High performance pulsed storage circuit  
The application discloses state storage circuitry comprising: an operational data input for receiving input data, a diagnostic data input for receiving diagnostic data and a diagnostic select...
US20130332785 TESTING OF NON STUCK-AT FAULTS IN MEMORY  
A method for identifying non stuck-at faults in a read-only memory (ROM) includes generating a golden value of a victim cell, providing a fault-specific pattern through an aggressor cell,...
US20060248414 Method and system for BitMap Analysis System for high speed testing of memories  
A Bit Map Analysis System (BMAS) for high-speed memory testing. The BMAS reduces the amount of data transaction between the BIST and tester may be used in embedded memories, whether asynchronous...
US20090228748 Method to automatically determine host to LUN (logical unit number) path availability for multi path attached storage systems  
The present disclosure provides testing of a storage system. The test may compare the storage array controller LUNs which may be configured to be accessible by a host with the LUNs which are...
US20080141082 TEST MODE MULTI-BYTE PROGRAMMING WITH INTERNAL VERIFY AND POLLING FUNCTION  
A method, device, and processor-readable medium for testing semiconductor devices. A method for testing a semiconductor device comprises: a) entering a multi-byte programming mode; b) programming...
US20090282303 BUILT IN TEST CONTROLLER WITH A DOWNLOADABLE TESTING PROGRAM  
An apparatus comprising a processor and an internal memory. The processor may be configured to test an external memory using (i) a netlist and (ii) a testing program. The internal memory may be...
US20120102374 STORAGE DEVICE TESTING  
A storage device testing system (100) includes at least one 310 robotic arm (200) defining a first axis (205) substantially normal to a 300 floor surface (10). The robotic arm is operable to...
US20070168775 Programmable Memory Test Controller  
Providing a programmable test controller integrated along with a random access memory (RAM). The programmable test controller can be programmed to test desired memory locations. Due to such a...
US20130290797 NON-VOLATILE MEMORY (NVM) RESET SEQUENCE WITH BUILT-IN READ CHECK  
A new, robust non-volatile memory (NVM) reset sequence is provided in accordance with at least one embodiment, which, after reading a Test NVM portion and overwriting NVM configuration registers'...
US20080195901 OP-CODE BASED BUILT-IN-SELF-TEST  
A built-in-self-test (BIST) system for testing a memory that includes a scheduler module that generates a first test algorithm based on a set of operational codes. Each operational code defines a...
US20070260946 Nonvolatile memory device comprising a programming and deletion checking option  
A method and circuitry for checking the programming (P) and deletion (L) operations of memory cells (5) in a nonvolatile memory device (1). Parallel to the programming (P) or deletion (L)...
US20090313511 SEMICONDUCTOR DEVICE TESTING  
A semiconductor device test circuit includes a data producing unit to produce first test data to be fed into a semiconductor device, and expected value data; a first data retaining unit to retain...